[Intel-gfx] [PATCH] drm/i915/gt: Restrict gen7 w/a batch to Haswell

[Mika Kuoppala]

Chris Wilson <chris at chris-wilson.co.uk> writes:

> The residual w/a batch is casing system instablity on Ivybridge and
> Baytrail under some workloads, so disable until resolved.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/1405
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan at intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodunrin at intel.com>
> Cc: Jani Nikula <jani.nikula at linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>

Acked-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 1424582e4a9b..fdc3f10e12aa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -2088,7 +2088,7 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine)
>  
>  	GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
>  
> -	if (IS_GEN(engine->i915, 7) && engine->class == RENDER_CLASS) {
> +	if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) {
>  		err = gen7_ctx_switch_bb_init(engine);
>  		if (err)
>  			goto err_ring_unpin;
> -- 
> 2.20.1