[Intel-gfx] [PATCH v2 3/6] drm/i915: Add Wa_1604278689:icl,ehl

[Souza, Jose]

On Wed, 2020-03-11 at 09:22 -0700, Matt Roper wrote:
> The bspec description for this workaround tells us to program
> 0xFFFF_FFFF into both FBC_RT_BASE_ADDR_REGISTER_* registers, but
> we've
> previously found that this leads to failures in CI.  Our suspicion is
> that the failures are caused by this valid turning on the "address
> valid
> bit" even though we're intentionally supplying an invalid address.
> Experimentation has shown that setting all bits _except_ for the
> RT_VALID bit seems to avoid these failures.
> 
> v2:
>  - Mask off the RT_VALID bit.  Experimentation with CI trybot
> indicates
>    that this is necessary to avoid reset failures on BCS.
> 
> v3:
>  - Program RT_BASE before RT_BASE_UPPER so that the valid bit is
> turned
>    off by the first write.  (Chris)

Match BSpec, if issue above are solved:

Reviewed-by: José Roberto de
Souza <jose.souza at intel.com>


> 
> Bspec: 11388
> Bspec: 33451
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
>  drivers/gpu/drm/i915/i915_reg.h             | 1 +
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3e352e2a5b79..3bbd89294279 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -575,6 +575,12 @@ static void icl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
>  	/* allow headerless messages for preemptible GPGPU context */
>  	WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
>  			  GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
> +
> +	/* Wa_1604278689:icl,ehl */
> +	wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
> +	wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
> +			   0, /* write-only register; skip validation
> */
> +			   0xFFFFFFFF);
>  }
>  
>  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 79ae9654dac9..92ae96cf5b64 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3285,6 +3285,7 @@ static inline bool
> i915_mmio_reg_valid(i915_reg_t reg)
>  
>  /* Framebuffer compression for Ivybridge */
>  #define IVB_FBC_RT_BASE			_MMIO(0x7020)
> +#define IVB_FBC_RT_BASE_UPPER		_MMIO(0x7024)
>  
>  #define IPS_CTL		_MMIO(0x43408)
>  #define   IPS_ENABLE	(1 << 31)