[Intel-gfx] [PATCH 05/13] drm/i915: Use REG_FIELD_PREP() & co. for TRANS_DDI_FUNC_CTL2

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

Clean up the TRANS_DDI_FUNC_CTL2 programming/readout by
using REG_FIELD_PREP() & co.

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  6 ++----
 drivers/gpu/drm/i915/i915_reg.h          | 10 ++++------
 2 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 39f3e9452aad..8bb6c583abb8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1573,9 +1573,7 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
 				master_select = master_transcoder + 1;
 
 			ctl2 |= PORT_SYNC_MODE_ENABLE |
-				(PORT_SYNC_MODE_MASTER_SELECT(master_select) &
-				 PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
-				PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
+				PORT_SYNC_MODE_MASTER_SELECT(master_select);
 		}
 
 		intel_de_write(dev_priv,
@@ -3854,7 +3852,7 @@ static enum transcoder transcoder_master_readout(struct drm_i915_private *dev_pr
 	if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
 		return INVALID_TRANSCODER;
 
-	master_select = ctl2 & PORT_SYNC_MODE_MASTER_SELECT_MASK;
+	master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
 
 	if (master_select == 0)
 		return TRANSCODER_EDP;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 309cb7d96b35..fc5c00bfed87 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9726,12 +9726,10 @@ enum skl_power_gate {
 #define _TRANS_DDI_FUNC_CTL2_EDP	0x6f404
 #define _TRANS_DDI_FUNC_CTL2_DSI0	0x6b404
 #define _TRANS_DDI_FUNC_CTL2_DSI1	0x6bc04
-#define TRANS_DDI_FUNC_CTL2(tran)	_MMIO_TRANS2(tran, \
-						     _TRANS_DDI_FUNC_CTL2_A)
-#define  PORT_SYNC_MODE_ENABLE			(1 << 4)
-#define  PORT_SYNC_MODE_MASTER_SELECT(x)	((x) << 0)
-#define  PORT_SYNC_MODE_MASTER_SELECT_MASK	(0x7 << 0)
-#define  PORT_SYNC_MODE_MASTER_SELECT_SHIFT	0
+#define TRANS_DDI_FUNC_CTL2(tran)	_MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A)
+#define  PORT_SYNC_MODE_ENABLE			REG_BIT(4)
+#define  PORT_SYNC_MODE_MASTER_SELECT_MASK	REG_GENMASK(2, 0)
+#define  PORT_SYNC_MODE_MASTER_SELECT(x)	REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
 
 /* DisplayPort Transport Control */
 #define _DP_TP_CTL_A			0x64040
-- 
2.24.1