[Intel-gfx] [PATCH v5 6/7] drm/i915/dp: Register definition for DP compliance register

[Manasi Navare]

On Mon, Mar 16, 2020 at 04:07:58PM +0530, Animesh Manna wrote:
> DP_COMP_CTL and DP_COMP_PAT register used to program DP
> compliance pattern.
> 
> v1: Initial patch.
> v2: used pipe instead of port in macro definition. [Manasi]
> 
> Reviewed-by: Manasi Navare <manasi.d.navare at intel.com>
> Signed-off-by: Animesh Manna <animesh.manna at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 309cb7d96b35..e93b90e17573 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9792,6 +9792,26 @@ enum skl_power_gate {
>  #define  DDI_BUF_BALANCE_LEG_ENABLE	(1 << 31)
>  #define DDI_BUF_TRANS_HI(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>  
> +/* DDI DP Compliance Control */
> +#define DDI_DP_COMP_CTL_A			0x605F0
> +#define DDI_DP_COMP_CTL_B			0x615F0
> +#define DDI_DP_COMP_CTL(pipe) _MMIO_PORT(pipe, DDI_DP_COMP_CTL_A, \
> +					 DDI_DP_COMP_CTL_B)

Since its pipe based, please try to use _MMIO_PIPE2 like in the def
of PIPECONF

> +#define  DDI_DP_COMP_CTL_ENABLE			(1 << 31)
> +#define  DDI_DP_COMP_CTL_D10_2			(0 << 28)
> +#define  DDI_DP_COMP_CTL_SCRAMBLED_0		(1 << 28)
> +#define  DDI_DP_COMP_CTL_PRBS7			(2 << 28)
> +#define  DDI_DP_COMP_CTL_CUSTOM80		(3 << 28)
> +#define  DDI_DP_COMP_CTL_HBR2			(4 << 28)
> +#define  DDI_DP_COMP_CTL_SCRAMBLED_1		(5 << 28)
> +#define  DDI_DP_COMP_CTL_HBR2_RESET		(0xFC << 0)
> +
> +/* DDI DP Compliance Pattern */
> +#define DDI_DP_COMP_PAT_A			0x605F4
> +#define DDI_DP_COMP_PAT_B			0x615F4
> +#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, DDI_DP_COMP_PAT_A, \
> +					     DDI_DP_COMP_PAT_B) + (i) * 4)

Same here , see if you can use _MMIO_PIPE2 and if the offsets work corectly for
all 4 pipes _A, _B, _C, _D

In both cases, might not even need to define _B

Manasi

> +
>  /* Sideband Interface (SBI) is programmed indirectly, via
>   * SBI_ADDR, which contains the register offset; and SBI_DATA,
>   * which contains the payload */
> -- 
> 2.24.0
>