[Intel-gfx] [PATCH v7 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type
kbuild test robot
lkp at intel.com
Tue Mar 17 03:42:43 UTC 2020
Hi Ankit,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20200316]
[cannot apply to v5.6-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Ankit-Navik/Dynamic-EU-configuration-of-Slice-Sub-slice-EU/20200317-070836
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.5.0-5) 7.5.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp at intel.com>
All warnings (new ones prefixed by >>):
drivers/gpu/drm/i915/intel_device_info.c: In function 'intel_device_info_runtime_init':
>> drivers/gpu/drm/i915/intel_device_info.c:1061:24: warning: assignment discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
dev_priv->opt_config = chv_config;
^
drivers/gpu/drm/i915/intel_device_info.c:1073:25: warning: assignment discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
dev_priv->opt_config = glk_gt1_config;
^
drivers/gpu/drm/i915/intel_device_info.c:1078:25: warning: assignment discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
dev_priv->opt_config = kbl_gt2_config;
^
drivers/gpu/drm/i915/intel_device_info.c:1083:25: warning: assignment discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
dev_priv->opt_config = kbl_gt3_config;
^
vim +/const +1061 drivers/gpu/drm/i915/intel_device_info.c
929
930 /**
931 * intel_device_info_runtime_init - initialize runtime info
932 * @dev_priv: the i915 device
933 *
934 * Determine various intel_device_info fields at runtime.
935 *
936 * Use it when either:
937 * - it's judged too laborious to fill n static structures with the limit
938 * when a simple if statement does the job,
939 * - run-time checks (eg read fuse/strap registers) are needed.
940 *
941 * This function needs to be called:
942 * - after the MMIO has been setup as we are reading registers,
943 * - after the PCH has been detected,
944 * - before the first usage of the fields it can tweak.
945 */
946 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
947 {
948 struct intel_device_info *info = mkwrite_device_info(dev_priv);
949 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
950 enum pipe pipe;
951
952 if (INTEL_GEN(dev_priv) >= 10) {
953 for_each_pipe(dev_priv, pipe)
954 runtime->num_scalers[pipe] = 2;
955 } else if (IS_GEN(dev_priv, 9)) {
956 runtime->num_scalers[PIPE_A] = 2;
957 runtime->num_scalers[PIPE_B] = 2;
958 runtime->num_scalers[PIPE_C] = 1;
959 }
960
961 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
962
963 if (INTEL_GEN(dev_priv) >= 11)
964 for_each_pipe(dev_priv, pipe)
965 runtime->num_sprites[pipe] = 6;
966 else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
967 for_each_pipe(dev_priv, pipe)
968 runtime->num_sprites[pipe] = 3;
969 else if (IS_BROXTON(dev_priv)) {
970 /*
971 * Skylake and Broxton currently don't expose the topmost plane as its
972 * use is exclusive with the legacy cursor and we only want to expose
973 * one of those, not both. Until we can safely expose the topmost plane
974 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
975 * we don't expose the topmost plane at all to prevent ABI breakage
976 * down the line.
977 */
978
979 runtime->num_sprites[PIPE_A] = 2;
980 runtime->num_sprites[PIPE_B] = 2;
981 runtime->num_sprites[PIPE_C] = 1;
982 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
983 for_each_pipe(dev_priv, pipe)
984 runtime->num_sprites[pipe] = 2;
985 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
986 for_each_pipe(dev_priv, pipe)
987 runtime->num_sprites[pipe] = 1;
988 }
989
990 if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) &&
991 HAS_PCH_SPLIT(dev_priv)) {
992 u32 fuse_strap = I915_READ(FUSE_STRAP);
993 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
994
995 /*
996 * SFUSE_STRAP is supposed to have a bit signalling the display
997 * is fused off. Unfortunately it seems that, at least in
998 * certain cases, fused off display means that PCH display
999 * reads don't land anywhere. In that case, we read 0s.
1000 *
1001 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1002 * should be set when taking over after the firmware.
1003 */
1004 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1005 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1006 (HAS_PCH_CPT(dev_priv) &&
1007 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1008 drm_info(&dev_priv->drm,
1009 "Display fused off, disabling\n");
1010 info->pipe_mask = 0;
1011 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
1012 drm_info(&dev_priv->drm, "PipeC fused off\n");
1013 info->pipe_mask &= ~BIT(PIPE_C);
1014 }
1015 } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
1016 u32 dfsm = I915_READ(SKL_DFSM);
1017 u8 enabled_mask = info->pipe_mask;
1018
1019 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
1020 enabled_mask &= ~BIT(PIPE_A);
1021 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
1022 enabled_mask &= ~BIT(PIPE_B);
1023 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
1024 enabled_mask &= ~BIT(PIPE_C);
1025 if (INTEL_GEN(dev_priv) >= 12 &&
1026 (dfsm & TGL_DFSM_PIPE_D_DISABLE))
1027 enabled_mask &= ~BIT(PIPE_D);
1028
1029 /*
1030 * At least one pipe should be enabled and if there are
1031 * disabled pipes, they should be the last ones, with no holes
1032 * in the mask.
1033 */
1034 if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
1035 drm_err(&dev_priv->drm,
1036 "invalid pipe fuse configuration: enabled_mask=0x%x\n",
1037 enabled_mask);
1038 else
1039 info->pipe_mask = enabled_mask;
1040
1041 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
1042 info->display.has_hdcp = 0;
1043
1044 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
1045 info->display.has_fbc = 0;
1046
1047 if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
1048 info->display.has_csr = 0;
1049
1050 if (INTEL_GEN(dev_priv) >= 10 &&
1051 (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
1052 info->display.has_dsc = 0;
1053 }
1054
1055 /* Initialize slice/subslice/EU info */
1056 if (IS_HASWELL(dev_priv))
1057 hsw_sseu_info_init(dev_priv);
1058 else if (IS_CHERRYVIEW(dev_priv)) {
1059 cherryview_sseu_info_init(dev_priv);
1060 BUILD_BUG_ON(ARRAY_SIZE(chv_config) != LOAD_TYPE_LAST);
> 1061 dev_priv->opt_config = chv_config;
1062 }
1063 else if (IS_BROADWELL(dev_priv))
1064 bdw_sseu_info_init(dev_priv);
1065 else if (IS_GEN(dev_priv, 9)) {
1066 gen9_sseu_info_init(dev_priv);
1067
1068 switch (info->gt) {
1069 default: /* fall through */
1070 case 1:
1071 BUILD_BUG_ON(ARRAY_SIZE(glk_gt1_config) !=
1072 LOAD_TYPE_LAST);
1073 dev_priv->opt_config = glk_gt1_config;
1074 break;
1075 case 2:
1076 BUILD_BUG_ON(ARRAY_SIZE(kbl_gt2_config) !=
1077 LOAD_TYPE_LAST);
1078 dev_priv->opt_config = kbl_gt2_config;
1079 break;
1080 case 3:
1081 BUILD_BUG_ON(ARRAY_SIZE(kbl_gt3_config) !=
1082 LOAD_TYPE_LAST);
1083 dev_priv->opt_config = kbl_gt3_config;
1084 break;
1085 }
1086 }
1087 else if (IS_GEN(dev_priv, 10))
1088 gen10_sseu_info_init(dev_priv);
1089 else if (IS_GEN(dev_priv, 11))
1090 gen11_sseu_info_init(dev_priv);
1091 else if (INTEL_GEN(dev_priv) >= 12)
1092 gen12_sseu_info_init(dev_priv);
1093
1094 if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
1095 drm_info(&dev_priv->drm,
1096 "Disabling ppGTT for VT-d support\n");
1097 info->ppgtt_type = INTEL_PPGTT_NONE;
1098 }
1099
1100 runtime->rawclk_freq = intel_read_rawclk(dev_priv);
1101 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
1102
1103 /* Initialize command stream timestamp frequency */
1104 runtime->cs_timestamp_frequency_khz =
1105 read_timestamp_frequency(dev_priv);
1106 if (runtime->cs_timestamp_frequency_khz) {
1107 runtime->cs_timestamp_period_ns =
1108 div_u64(1e6, runtime->cs_timestamp_frequency_khz);
1109 drm_dbg(&dev_priv->drm,
1110 "CS timestamp wraparound in %lldms\n",
1111 div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns,
1112 S32_MAX),
1113 USEC_PER_SEC));
1114 }
1115 }
1116
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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