[Intel-gfx] [PATCH v20 00/10] SAGV support for Gen12+

[Stanislav Lisovskiy]

For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.

v17: Had to rebase the whole series.

v19: Added some new patches in between, rebased

v20: Added new patches and rebased the series

Stanislav Lisovskiy (10):
  drm/i915: Start passing latency as parameter
  drm/i915: Eliminate magic numbers "0" and "1" from color plane
  drm/i915: Introduce skl_plane_wm_level accessor.
  drm/i915: Add intel_atomic_get_bw_*_state helpers
  drm/i915: Extract gen specific functions from intel_can_enable_sagv
  drm/i915: Add proper SAGV support for TGL+
  drm/i915: Added required new PCode commands
  drm/i915: Rename bw_state to new_bw_state
  drm/i915: Restrict qgv points which don't have enough bandwidth.
  drm/i915: Enable SAGV support for Gen12

 drivers/gpu/drm/i915/display/intel_bw.c       | 200 +++++--
 drivers/gpu/drm/i915/display/intel_bw.h       |  24 +
 drivers/gpu/drm/i915/display/intel_display.c  |  29 +-
 .../drm/i915/display/intel_display_types.h    |  12 +
 drivers/gpu/drm/i915/i915_reg.h               |   4 +
 drivers/gpu/drm/i915/intel_pm.c               | 555 +++++++++++++++---
 drivers/gpu/drm/i915/intel_pm.h               |   6 +-
 drivers/gpu/drm/i915/intel_sideband.c         |   2 +
 8 files changed, 690 insertions(+), 142 deletions(-)

-- 
2.24.1.485.gad05a3d8e5