[Intel-gfx] [PATCH 00/23] Introduce Rocket Lake

[Matt Roper]

Rocket Lake (RKL) is another gen12 platform, so the driver support is
mostly a straightforward evolution of our existing Tiger Lake support.

One area of this patch series that's a bit non-intuitive and warrants
some extra explanation is the output handling.  All four of RKL's output
ports use combo PHYs, but the hardware guys have recycled the naming
scheme from Tiger Lake.  The DDI's are still named "A, B, TC1, and TC2"
even though none of them are actually connected to Type-C PHYs on this
platform.  From a register offset perspective, these four DDIs are
effectively A, B, D, and E (skipping over the register range that would
usually be used for a "C" instance of the DDI).  However the PHYs
attached to those DDIs do *not* skip the "C" instance, so we wind up
with the following output relationships:

        DDI-A   (port A) <-> PHY-A
        DDI-B   (port B) <-> PHY-B
        DDI-TC1 (port D) <-> PHY-C
        DDI-TC2 (port E) <-> PHY-D

Given that most of our past platforms have straight DDI==PHY mappings,
extra care is needed to ensure we use the proper namespace (port or phy)
when programming various output-related registers.


Aditya Swarup (1):
  drm/i915/rkl: Don't try to read out DSI transcoders

José Roberto de Souza (1):
  drm/i915/rkl: Disable PSR2

Lucas De Marchi (1):
  drm/i915/rkl: provide port/phy mapping for vbt

Matt Roper (20):
  drm/i915/rkl: Add RKL platform info and PCI ids
  x86/gpu: add RKL stolen memory support
  drm/i915/rkl: Re-use TGL GuC/HuC firmware
  drm/i915/rkl: Load DMC firmware for Rocket Lake
  drm/i915/rkl: Add PCH support
  drm/i915/rkl: Update memory bandwidth parameters
  drm/i915/rkl: Limit number of universal planes to 5
  drm/i915/rkl: Add power well support
  drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
  drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
  drm/i915/rkl: Add cdclk support
  drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
  drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs
  drm/i915/rkl: Setup ports/phys
  drm/i915/rkl: Add DDC pin mapping
  drm/i915/rkl: Don't try to access transcoder D
  drm/i915/rkl: Handle comp master/slave relationships for PHYs
  drm/i915/rkl: Add DPLL4 support
  drm/i915/rkl: Handle HTI
  drm/i915/rkl: Add initial workarounds

 arch/x86/kernel/early-quirks.c                |   1 +
 drivers/gpu/drm/i915/display/intel_bios.c     |  72 ++++--
 drivers/gpu/drm/i915/display/intel_bw.c       |  10 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  54 ++++-
 .../gpu/drm/i915/display/intel_combo_phy.c    |  55 +++--
 drivers/gpu/drm/i915/display/intel_csr.c      |  10 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  18 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  82 +++++--
 .../drm/i915/display/intel_display_power.c    | 229 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dp.c       |   8 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  50 +++-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   1 +
 drivers/gpu/drm/i915/display/intel_hdmi.c     |  22 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  15 ++
 drivers/gpu/drm/i915/display/intel_sprite.c   |  22 +-
 drivers/gpu/drm/i915/display/intel_sprite.h   |  11 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |   4 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  88 ++++---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c      |   3 +
 drivers/gpu/drm/i915/i915_drv.h               |  13 +
 drivers/gpu/drm/i915/i915_irq.c               |  10 +-
 drivers/gpu/drm/i915/i915_pci.c               |  13 +
 drivers/gpu/drm/i915/i915_reg.h               |  33 ++-
 drivers/gpu/drm/i915/intel_device_info.c      |   6 +-
 drivers/gpu/drm/i915/intel_device_info.h      |   2 +
 drivers/gpu/drm/i915/intel_pch.c              |   8 +-
 include/drm/i915_pciids.h                     |   9 +
 27 files changed, 702 insertions(+), 147 deletions(-)

-- 
2.24.1