[Intel-gfx] [PATCH v2 0/3] Steer multicast register workaround verification

Matt Roper matthew.d.roper at intel.com
Sat May 2 04:57:41 UTC 2020

We're seeing some CI errors indicating that a workaround did not apply
properly on EHL/JSL.  The workaround in question is updating a multicast
register, the failures are only seen on specific CI machines, and the
failures only seem to happen on resets and such rather than on initial
driver load.  It seems likely that the culprit here is failure to steer
the multicast register readback on a SKU that has slice0 / subslice0
fused off.

This series makes a couple changes:
 * Ensure setup of MCR steering is done at the beginning of the RCS
   engine workaround list, not just the general GT workaround list.
 * New multicast ranges are added for gen11 and gen12.  Sadly this
   information is still missing from the bspec (just like the updated
   forcewake tables).  The hardware guys have given us a spreadsheet
   with both the forcewake and the multicast information while they work
   on getting the spec properly updated, so that's where the new ranges
   come from.

In addition to MCR and forcewake, there's supposed to be some more bspec
updates coming soon that deal with steering (i.e., different MCR ranges
should actually be using different registers to steer rather than just
the 0xFDC register we're familiar with); I don't have the full details
on that yet, so those updates will have to wait until we actually have
an updated spec.

References: https://gitlab.freedesktop.org/drm/intel/issues/1222

Matt Roper (3):
  drm/i915: Setup multicast register steering for all gen >= 10
  drm/i915: Setup MCR steering for RCS engine workarounds
  drm/i915: Add MCR ranges for gen11 and gen12

 drivers/gpu/drm/i915/gt/intel_workarounds.c | 57 ++++++++++++++++-----
 1 file changed, 45 insertions(+), 12 deletions(-)


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