[Intel-gfx] [PATCH v2 3/3] drm/i915: Add MCR ranges for gen11 and gen12

[Matt Roper]

The multicast register ranges are slightly different for gen11 and gen12
than the table we have for gen8.  This information never got updated in
the bspec, so this patch is based on a spreadsheet provided by the
hardware team while they work on getting the official documentation
updated.

Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 45 ++++++++++++++++++---
 1 file changed, 39 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b11b83546696..370607514e7b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1668,10 +1668,12 @@ create_scratch(struct i915_address_space *vm, int count)
 	return ERR_PTR(err);
 }
 
-static const struct {
+struct mcr_range {
 	u32 start;
 	u32 end;
-} mcr_ranges_gen8[] = {
+};
+
+static const struct mcr_range mcr_ranges_gen8[] = {
 	{ .start = 0x5500, .end = 0x55ff },
 	{ .start = 0x7000, .end = 0x7fff },
 	{ .start = 0x9400, .end = 0x97ff },
@@ -1680,11 +1682,42 @@ static const struct {
 	{},
 };
 
+static const struct mcr_range mcr_ranges_gen11[] = {
+	{ .start = 0x5500,  .end = 0x55ff },
+	{ .start = 0x7000,  .end = 0x7fff },
+	{ .start = 0x8140,  .end = 0x815f },
+	{ .start = 0x8c00,  .end = 0x8cff },
+	{ .start = 0x94d0,  .end = 0x955f },
+	{ .start = 0xb000,  .end = 0xb3ff },
+	{ .start = 0xdf00,  .end = 0xe8ff },
+	{ .start = 0x24400, .end = 0x24fff },
+	{},
+};
+
+static const struct mcr_range mcr_ranges_gen12[] = {
+	{ .start = 0xb00,   .end = 0xbff },
+	{ .start = 0x1000,  .end = 0x1fff },
+	{ .start = 0x8150,  .end = 0x815f },
+	{ .start = 0x8700,  .end = 0x87ff },
+	{ .start = 0x9520,  .end = 0x955f },
+	{ .start = 0xb100,  .end = 0xb3ff },
+	{ .start = 0xde80,  .end = 0xe8ff },
+	{ .start = 0x24a00, .end = 0x24a7f },
+	{},
+};
+
 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
 {
+	const struct mcr_range *range_list;
 	int i;
 
-	if (INTEL_GEN(i915) < 8)
+	if (INTEL_GEN(i915) >= 12)
+		range_list = mcr_ranges_gen12;
+	else if (INTEL_GEN(i915) >= 11)
+		range_list = mcr_ranges_gen11;
+	else if (INTEL_GEN(i915) >= 8)
+		range_list = mcr_ranges_gen8;
+	else
 		return false;
 
 	/*
@@ -1692,9 +1725,9 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
 	 * which only controls CPU initiated MMIO. Routing does not
 	 * work for CS access so we cannot verify them on this path.
 	 */
-	for (i = 0; mcr_ranges_gen8[i].start; i++)
-		if (offset >= mcr_ranges_gen8[i].start &&
-		    offset <= mcr_ranges_gen8[i].end)
+	for (i = 0; range_list[i].start; i++)
+		if (offset >= range_list[i].start &&
+		    offset <= range_list[i].end)
 			return true;
 
 	return false;
-- 
2.24.1