[Intel-gfx] [PATCH 2/9] drm/i915/gen12: Fix HDC pipeline flush

[Chris Wilson]

Quoting Mika Kuoppala (2020-04-30 16:47:28)
> HDC pipeline flush is bit on the first dword of
> the PIPE_CONTROL, not the second. Make it so.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_engine.h       | 23 +++++++++++----
>  drivers/gpu/drm/i915/gt/intel_gpu_commands.h |  2 +-
>  drivers/gpu/drm/i915/gt/intel_lrc.c          | 30 ++++++++++----------
>  3 files changed, 33 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index d10e52ff059f..f449171ae808 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -241,19 +241,24 @@ void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
>  void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
>                                     struct drm_printer *p);
>  
> -static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
> +static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
>  {
>         memset(batch, 0, 6 * sizeof(u32));
>  
> -       batch[0] = GFX_OP_PIPE_CONTROL(6);
> -       batch[1] = flags;
> +       batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0;
> +       batch[1] = flags1;
>         batch[2] = offset;
>  
>         return batch + 6;
>  }
>  
> +static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
> +{
> +       return gen12_emit_pipe_control(batch, 0, flags, offset);

We always call into older; the gen prefix indicates the earliest the
function is usable.
-Chris