[Intel-gfx] [PATCH 7/9] drm/i915/gen12: Wait on previous flush on invalidate

Chris Wilson chris at chris-wilson.co.uk
Sun May 3 21:31:22 UTC 2020

Quoting Mika Kuoppala (2020-04-30 16:47:33)
> Flush enable bit is a sync point which makes this
> pipecontrol to wait that everything on a previous
> pipe control are flushed. Enable it to make
> sure that our invalidates doesn't overlap.

Not sold. We terminated the previous context with a serialising flush;
the pipe should be idle... But what about preemption, hmm? But then you
have preemption between batches past the invalidate point, and so it
must all be safely restored from context.

So the primarily concern here is with state being overwritten by GTT

Still not sold.

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