[Intel-gfx] [PATCH 4/4] drm/i915/gen12: Invalidate aux table entries forcibly

[Chris Wilson]

Quoting Mika Kuoppala (2020-05-06 17:53:10)
> Aux table invalidation can fail on update. So
> next access may cause memory access to be into stale entry.
> 
> Proposed workaround is to invalidate entries between
> all batchbuffers.
> 
> v2: correct register address (Yang)
> v3: respect the order (Chris)
> 
> References bspec#43904, hsdes#1809175790
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Chuansheng Liu <chuansheng.liu at intel.com>
> Cc: Rafael Antognolli <rafael.antognolli at intel.com>
> Cc: Yang A Shi <yang.a.shi at intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> Acked-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c | 16 +++++++++++++++-
>  drivers/gpu/drm/i915/i915_reg.h     |  2 ++
>  2 files changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index e1235d504837..bbdb0e2a4571 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -4539,6 +4539,17 @@ static u32 preparser_disable(bool state)
>         return MI_ARB_CHECK | 1 << 8 | state;
>  }
>  
> +static u32 *
> +gen12_emit_aux_table_inv(struct i915_request *rq, u32 *cs)
> +{
> +       *cs++ = MI_LOAD_REGISTER_IMM(1);
> +       *cs++ = i915_mmio_reg_offset(GEN12_GFX_CCS_AUX_NV);
> +       *cs++ = AUX_INV;
> +       *cs++ = MI_NOOP;
> +
> +       return cs;
> +}
> +
>  static int gen12_emit_flush_render(struct i915_request *request,
>                                    u32 mode)
>  {
> @@ -4587,7 +4598,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
>  
>                 flags |= PIPE_CONTROL_CS_STALL;
>  
> -               cs = intel_ring_begin(request, 8);
> +               cs = intel_ring_begin(request, 8 + 4);
>                 if (IS_ERR(cs))
>                         return PTR_ERR(cs);
>  
> @@ -4600,6 +4611,9 @@ static int gen12_emit_flush_render(struct i915_request *request,
>  
>                 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
>  
> +               /* hsdes: 1809175790 */
> +               cs = gen12_emit_aux_table_inv(request, cs);

It is worth mentioning that we do not fix up the EMIT_INVALIDATE for the
actual physical engine a virtual request may run on. Not a problem until
you try to support other engines. Pray for a quick HW fix.
-Chris