[Intel-gfx] [PATCH] drm/i915: Force pte cacheline to main memory

Chris Wilson chris at chris-wilson.co.uk
Mon May 11 16:16:52 UTC 2020

Quoting Chris Wilson (2020-05-11 17:13:52)
> Quoting Mika Kuoppala (2020-05-11 17:08:03)
> > We have problems of tgl not seeing a valid pte entry
> > when iommu is enabled. Add heavy handed flushing
> > of entry modification by flushing the cpu, cacheline
> > and then wcb. This forces the pte out to main memory
> > past this point regarless of promises of coherency.
> > 
> > This is an evolution of an experimental patch from
> > Chris Wilson of adding wmb for coherent partners,
> > by adding a clflush to force the cache->memory step.
> > 
> > Testcase: igt/gem_exec_fence/parallel
> > Cc: Chris Wilson <chris at chris-wilson.co.uk>
> > Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> Not only does it help tgl, but it is also helping with a coherency
> problem on Braswell. We see similar problems on gen9 and icl, and I have
> a trybot run to see if it helps with those.

It should be noted that Braswell is using WC kmaps of the PTE, so this
should not even be necessary... But if we drop the WC and keep the
clflush, it fails. Just to add to the confusion.

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