[Intel-gfx] [PATCH v8 4/7] drm/i915: Plane configuration affects CDCLK in Gen11+

[Manasi Navare]

On Thu, May 14, 2020 at 06:21:42PM +0300, Stanislav Lisovskiy wrote:
> From: Stanislav Lisovskiy <stanislav.lisovskiY at intel.com>
> 
> So lets support it.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare at intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a9ab66d97360..800ae3768841 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14569,7 +14569,7 @@ static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
>  	/* See {hsw,vlv,ivb}_plane_ratio() */
>  	return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
>  		IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
> -		IS_IVYBRIDGE(dev_priv);
> +		IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
>  }
>  
>  static int intel_atomic_check_planes(struct intel_atomic_state *state)
> -- 
> 2.24.1.485.gad05a3d8e5
> 
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