[Intel-gfx] [PATCH 6/6] drm/i915/selftests: Make the CS timestamp tests work on gen4-snb (sort of)
chris at chris-wilson.co.uk
Sun May 17 12:49:36 UTC 2020
Quoting Ville Syrjala (2020-03-02 14:39:43)
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> On pre-ivb the CS timestamp register is only present on RCS (despite
> what snb bspec claims). Let's test it.
> Also on ctg/elk/ilk the usable part of the timestamp is the UDW so
> let's read that instead of the LDW. On ctg/elk the 10 msbs of the LDW
> do actually work, but we configure cs_timestamp_frequency_hz as if
> they didn't so that we can treat ctg/elk the same as ilk.
> TODO: figure out why the results we get aren't reliable. On some
> iterations we can get totally wrong (though consistent) values,
> on other iterations the values are correct. And somehow changing
> the offsets into the hwsp also seems to affect the behaviour.
> Manually reading the register always seems fine, so feels like
> the problem has something to do with the store rather than the actual
> register read.
On i965gm, I get fairly random output from reading the CS_TIMESTAMP.
One step at a time, first let's get the test results for reading
CS_TIMESTAMP vs the updated rawclk and see how well we fare across the
farm. Then we might see if there's a pattern here.
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