[Intel-gfx] [PATCH 1/2] drm/i915/display/tgl: Disable FBC with PSR2

[Souza, Jose]

On Thu, 2020-11-05 at 21:57 +0530, Shankar, Uma wrote:
> 
> > -----Original Message-----
> > From: Souza, Jose <jose.souza at intel.com>
> > Sent: Thursday, November 5, 2020 9:38 PM
> > To: Shankar, Uma <uma.shankar at intel.com>; intel-gfx at lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/display/tgl: Disable FBC with PSR2
> > 
> > On Thu, 2020-11-05 at 01:26 +0530, Uma Shankar wrote:
> > > There are some corner cases wrt underrun when we enable FBC with PSR2
> > > on TGL. Recommendation from hardware is to keep this combination
> > > disabled.
> > 
> > Do you have any references to this? HSD? BSpec?
> 
> Hi Jose,
> Below is the HSD for the same:
> https://hsdes.intel.com/appstore/article/#/14010260002
> 
> Will add the link in patch as well.

I have commented in that HSD in the past, it looked to me that we were not affected by that as that HSD refers to GEN11+. Also that HSD looks odd
there is no real report of issue there.

Are you sure that the FBC underruns are because of PSR2? Not all TGL systems in CI have a PSR2 panel, please make sure we are not disabling FBC in
vain.

> 
> Regards,
> Uma Shankar
> > 
> > > 
> > > Signed-off-by: Uma Shankar <uma.shankar at intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++++++
> > >  1 file changed, 6 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index a5b072816a7b..32c411414908 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -799,6 +799,12 @@ static bool intel_fbc_can_activate(struct intel_crtc
> > *crtc)
> > >  	struct intel_fbc *fbc = &dev_priv->fbc;
> > >  	struct intel_fbc_state_cache *cache = &fbc->state_cache;
> > > 
> > > 
> > > 
> > > 
> > > +	if (dev_priv->psr.sink_psr2_support &&
> > > +	    IS_TIGERLAKE(dev_priv)) {
> > > +		fbc->no_fbc_reason = "not supported with PSR2";
> > > +		return false;
> > > +	}
> > > +
> > >  	if (!intel_fbc_can_enable(dev_priv))
> > >  		return false;
> > > 
> > > 
> > > 
> > > 
>