[Intel-gfx] [PATCH] drm/i915: Correctly set SFC capability for video engines

[Chris Wilson]

Quoting Tvrtko Ursulin (2020-11-06 09:30:05)
> 
> On 06/11/2020 01:18, Daniele Ceraolo Spurio wrote:
> > From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com>
> > 
> > SFC capability of video engines is not set correctly because i915
> > is testing for incorrect bits.
> > 
> > Fixes: c5d3e39caa45 ("drm/i915: Engine discovery query")
> > Cc: Matt Roper <matthew.d.roper at intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> > Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com>
> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> > ---
> >   drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 ++-
> >   1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index 3fb52fac0d5d..0b31670343f5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -372,7 +372,8 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
> >                * instances.
> >                */
> >               if ((INTEL_GEN(i915) >= 11 &&
> > -                  engine->gt->info.vdbox_sfc_access & engine->mask) ||
> > +                  (engine->gt->info.vdbox_sfc_access &
> > +                   BIT(engine->instance))) ||
> >                   (INTEL_GEN(i915) >= 9 && engine->instance == 0))
> >                       engine->uabi_capabilities |=
> >                               I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
> > 
> 
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Fixes: c5d3e39caa45 ("drm/i915: Engine discovery query")

Will push,
-Chris

> 
> Regards,
> 
> Tvrtko
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