[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg1: map/unmap pll clocks

[Patchwork]

== Series Details ==

Series: drm/i915/dg1: map/unmap pll clocks
URL   : https://patchwork.freedesktop.org/series/83592/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a589e37423a2 drm/i915/dg1: map/unmap pll clocks
-:187: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#187: FILE: drivers/gpu/drm/i915/display/intel_display.c:11014:
+	clk_sel = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);

-:254: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#254: FILE: drivers/gpu/drm/i915/i915_reg.h:10331:
+#define _DG1_PHY_DPLL_MAP(phy)				((phy) >= PHY_C ? DPLL_ID_DG1_DPLL2 : DPLL_ID_DG1_DPLL0)

-:260: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#260: FILE: drivers/gpu/drm/i915/i915_reg.h:10337:
+#define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	(_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))

-:261: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#261: FILE: drivers/gpu/drm/i915/i915_reg.h:10338:
+#define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))

-:262: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible side-effects?
#262: FILE: drivers/gpu/drm/i915/i915_reg.h:10339:
+#define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy) \
+	(((clk_sel) >> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + _DG1_PHY_DPLL_MAP(phy))

total: 0 errors, 4 warnings, 1 checks, 211 lines checked