[Intel-gfx] [PULL] drm-intel-fixes

[Vivi, Rodrigo]

> On Nov 12, 2020, at 4:32 PM, Dave Airlie <airlied at gmail.com> wrote:
> 
> On Fri, 13 Nov 2020 at 09:08, Rodrigo Vivi <rodrigo.vivi at intel.com> wrote:
>> 
>> Hi Dave and Daniel,
>> 
>> This is the same set as last week + couple new fixes targeting stable.
>> 
> 
> But I merged last weeks set and it's in rc3, maybe you can generate
> the pull request relative to origin/master or drm/drm-fixes because
> I'm not sure which bits to edit out here.

oh, of course... bad rebase on my part. Sorry...
Please ignore this one. I'm going to generate another one soon.

> 
> Dave.
> 
>> Thanks,
>> Rodrigo.
>> 
>> drm-intel-fixes-2020-11-12-1:
>> - GVT fixes including vGPU suspend/resume fixes and workaround for APL guest GPU hang.
>> - Fix set domain's cache coherency (Chris)
>> - Fixes around breadcrumbs (Chris)
>> - Fix encoder lookup during PSR atomic (Imre)
>> - Hold onto an explicit ref to i915_vma_work.pinned (Chris)
>> - Pull phys pread/pwrite implementations to the backend (Chris)
>> - Correctly set SFC capability for video engines
>> The following changes since commit 3cea11cd5e3b00d91caf0b4730194039b45c5891:
>> 
>>  Linux 5.10-rc2 (2020-11-01 14:43:51 -0800)
>> 
>> are available in the Git repository at:
>> 
>>  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2020-11-12-1
>> 
>> for you to fetch changes up to a4264790f4c2f0062d27d8173344c914bc7884e0:
>> 
>>  drm/i915: Correctly set SFC capability for video engines (2020-11-12 16:41:54 -0500)
>> 
>> ----------------------------------------------------------------
>> - GVT fixes including vGPU suspend/resume fixes and workaround for APL guest GPU hang.
>> - Fix set domain's cache coherency (Chris)
>> - Fixes around breadcrumbs (Chris)
>> - Fix encoder lookup during PSR atomic (Imre)
>> - Hold onto an explicit ref to i915_vma_work.pinned (Chris)
>> - Pull phys pread/pwrite implementations to the backend (Chris)
>> - Correctly set SFC capability for video engines
>> 
>> ----------------------------------------------------------------
>> Chris Wilson (6):
>>      drm/i915/gem: Flush coherency domains on first set-domain-ioctl
>>      drm/i915/gt: Use the local HWSP offset during submission
>>      drm/i915/gt: Expose more parameters for emitting writes into the ring
>>      drm/i915/gt: Flush xcs before tgl breadcrumbs
>>      drm/i915: Hold onto an explicit ref to i915_vma_work.pinned
>>      drm/i915/gem: Pull phys pread/pwrite implementations to the backend
>> 
>> Colin Xu (4):
>>      drm/i915/gvt: Allow zero out HWSP addr on hws_pga_write
>>      drm/i915/gvt: Set SNOOP for PAT3 on BXT/APL to workaround GPU BB hang
>>      drm/i915/gvt: Only pin/unpin intel_context along with workload
>>      drm/i915/gvt: Fix mmio handler break on BXT/APL.
>> 
>> Imre Deak (1):
>>      drm/i915: Fix encoder lookup during PSR atomic check
>> 
>> Matthew Auld (1):
>>      drm/i915/gem: Allow backends to override pread implementation
>> 
>> Venkata Sandeep Dhanalakota (1):
>>      drm/i915: Correctly set SFC capability for video engines
>> 
>> drivers/gpu/drm/i915/display/intel_psr.c         |  2 +-
>> drivers/gpu/drm/i915/gem/i915_gem_domain.c       | 28 ++++++------
>> drivers/gpu/drm/i915/gem/i915_gem_object_types.h |  2 +
>> drivers/gpu/drm/i915/gem/i915_gem_phys.c         | 55 ++++++++++++++++++++++++
>> drivers/gpu/drm/i915/gt/intel_engine.h           | 55 +++++++++++++++---------
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c        |  3 +-
>> drivers/gpu/drm/i915/gt/intel_lrc.c              | 31 +++++++++----
>> drivers/gpu/drm/i915/gt/intel_timeline.c         | 18 ++++----
>> drivers/gpu/drm/i915/gt/intel_timeline_types.h   |  2 +
>> drivers/gpu/drm/i915/gvt/handlers.c              | 47 ++++++++++++++++++--
>> drivers/gpu/drm/i915/gvt/scheduler.c             | 15 ++++---
>> drivers/gpu/drm/i915/i915_gem.c                  | 32 +++-----------
>> drivers/gpu/drm/i915/i915_vma.c                  |  6 ++-
>> 13 files changed, 204 insertions(+), 92 deletions(-)