[Intel-gfx] [PATCH v2 02/13] drm/edid: Parse MAX_FRL field from HFVSDB block

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal at intel.com>
> Sent: Sunday, November 1, 2020 3:37 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: dri-devel at lists.freedesktop.org; Shankar, Uma <uma.shankar at intel.com>;
> Kulkarni, Vandita <vandita.kulkarni at intel.com>; ville.syrjala at linux.intel.com;
> Sharma, Swati2 <swati2.sharma at intel.com>
> Subject: [PATCH v2 02/13] drm/edid: Parse MAX_FRL field from HFVSDB block
> 
> From: Swati Sharma <swati2.sharma at intel.com>
> 
> This patch parses MAX_FRL field to get the MAX rate in Gbps that the HDMI 2.1
> panel can support in FRL mode. Source need this field to determine the optimal
> rate between the source and sink during FRL training.
> 
> v2: Fixed minor bugs, and removed extra wrapper function (Uma Shankar)

Reviewed-by: Uma Shankar <uma.shankar at intel.com>

> Signed-off-by: Sharma, Swati2 <swati2.sharma at intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
> ---
>  drivers/gpu/drm/drm_edid.c  | 44 +++++++++++++++++++++++++++++++++++++
>  include/drm/drm_connector.h |  6 +++++
>  2 files changed, 50 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
> 631125b46e04..26797868ea5b 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4849,6 +4849,41 @@ static void drm_parse_vcdb(struct drm_connector
> *connector, const u8 *db)
>  		info->rgb_quant_range_selectable = true;  }
> 
> +static
> +void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8
> +*max_rate_per_lane) {
> +	switch (max_frl_rate) {
> +	case 1:
> +		*max_lanes = 3;
> +		*max_rate_per_lane = 3;
> +		break;
> +	case 2:
> +		*max_lanes = 3;
> +		*max_rate_per_lane = 6;
> +		break;
> +	case 3:
> +		*max_lanes = 4;
> +		*max_rate_per_lane = 6;
> +		break;
> +	case 4:
> +		*max_lanes = 4;
> +		*max_rate_per_lane = 8;
> +		break;
> +	case 5:
> +		*max_lanes = 4;
> +		*max_rate_per_lane = 10;
> +		break;
> +	case 6:
> +		*max_lanes = 4;
> +		*max_rate_per_lane = 12;
> +		break;
> +	case 0:
> +	default:
> +		*max_lanes = 0;
> +		*max_rate_per_lane = 0;
> +	}
> +}
> +
>  static void drm_parse_ycbcr420_deep_color_info(struct drm_connector
> *connector,
>  					       const u8 *db)
>  {
> @@ -4902,6 +4937,15 @@ static void drm_parse_hdmi_forum_vsdb(struct
> drm_connector *connector,
>  		}
>  	}
> 
> +	if (hf_vsdb[7]) {
> +		u8 max_frl_rate;
> +
> +		DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
> +		max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK)
> >> 4;
> +		drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
> +				&hdmi->max_frl_rate_per_lane);
> +	}
> +
>  	drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);  }
> 
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index
> 928136556174..f351bf10c076 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -207,6 +207,12 @@ struct drm_hdmi_info {
> 
>  	/** @y420_dc_modes: bitmap of deep color support index */
>  	u8 y420_dc_modes;
> +
> +	/** @max_frl_rate_per_lane: support fixed rate link */
> +	u8 max_frl_rate_per_lane;
> +
> +	/** @max_lanes: supported by sink */
> +	u8 max_lanes;
>  };
> 
>  /**
> --
> 2.17.1