[Intel-gfx] [CI 4/6] drm/i915/gt: Show all active timelines for debugging
Tvrtko Ursulin
tvrtko.ursulin at linux.intel.com
Thu Nov 19 18:08:49 UTC 2020
On 19/11/2020 16:56, Chris Wilson wrote:
> Include the active timelines for debugfs/i915_engine_info, so that we
> can see which have unready requests inflight which are not shown
> otherwise.
>
> Suggested-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Reviewd-by: Chris Wilson <chris at chris-wilson.co.uk>
Wrong paste, I believe I r-b-ed this one.
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Regards,
Tvrtko
> ---
> drivers/gpu/drm/i915/gt/intel_timeline.c | 80 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_timeline.h | 9 +++
> drivers/gpu/drm/i915/i915_debugfs.c | 16 ++---
> 3 files changed, 98 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
> index 7ea94d201fe6..512afacd2bdc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
> @@ -617,6 +617,86 @@ void intel_gt_fini_timelines(struct intel_gt *gt)
> GEM_BUG_ON(!list_empty(&timelines->hwsp_free_list));
> }
>
> +void intel_gt_show_timelines(struct intel_gt *gt,
> + struct drm_printer *m,
> + void (*show_request)(struct drm_printer *m,
> + const struct i915_request *rq,
> + const char *prefix,
> + int indent))
> +{
> + struct intel_gt_timelines *timelines = >->timelines;
> + struct intel_timeline *tl, *tn;
> + LIST_HEAD(free);
> +
> + spin_lock(&timelines->lock);
> + list_for_each_entry_safe(tl, tn, &timelines->active_list, link) {
> + unsigned long count, ready, inflight;
> + struct i915_request *rq, *rn;
> + struct dma_fence *fence;
> +
> + if (!mutex_trylock(&tl->mutex)) {
> + drm_printf(m, "Timeline %llx: busy; skipping\n",
> + tl->fence_context);
> + continue;
> + }
> +
> + intel_timeline_get(tl);
> + GEM_BUG_ON(!atomic_read(&tl->active_count));
> + atomic_inc(&tl->active_count); /* pin the list element */
> + spin_unlock(&timelines->lock);
> +
> + count = 0;
> + ready = 0;
> + inflight = 0;
> + list_for_each_entry_safe(rq, rn, &tl->requests, link) {
> + if (i915_request_completed(rq))
> + continue;
> +
> + count++;
> + if (i915_request_is_ready(rq))
> + ready++;
> + if (i915_request_is_active(rq))
> + inflight++;
> + }
> +
> + drm_printf(m, "Timeline %llx: { ", tl->fence_context);
> + drm_printf(m, "count: %lu, ready: %lu, inflight: %lu",
> + count, ready, inflight);
> + drm_printf(m, ", seqno: { current: %d, last: %d }",
> + *tl->hwsp_seqno, tl->seqno);
> + fence = i915_active_fence_get(&tl->last_request);
> + if (fence) {
> + drm_printf(m, ", engine: %s",
> + to_request(fence)->engine->name);
> + dma_fence_put(fence);
> + }
> + drm_printf(m, " }\n");
> +
> + if (show_request) {
> + list_for_each_entry_safe(rq, rn, &tl->requests, link)
> + show_request(m, rq, "", 2);
> + }
> +
> + mutex_unlock(&tl->mutex);
> + spin_lock(&timelines->lock);
> +
> + /* Resume list iteration after reacquiring spinlock */
> + list_safe_reset_next(tl, tn, link);
> + if (atomic_dec_and_test(&tl->active_count))
> + list_del(&tl->link);
> +
> + /* Defer the final release to after the spinlock */
> + if (refcount_dec_and_test(&tl->kref.refcount)) {
> + GEM_BUG_ON(atomic_read(&tl->active_count));
> + list_add(&tl->link, &free);
> + }
> + }
> + spin_unlock(&timelines->lock);
> +
> + list_for_each_entry_safe(tl, tn, &free, link)
> + __intel_timeline_free(&tl->kref);
> +}
> +
> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> #include "gt/selftests/mock_timeline.c"
> #include "gt/selftest_timeline.c"
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h b/drivers/gpu/drm/i915/gt/intel_timeline.h
> index 9882cd911d8e..634acebd0c4b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.h
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
> @@ -31,6 +31,8 @@
> #include "i915_syncmap.h"
> #include "intel_timeline_types.h"
>
> +struct drm_printer;
> +
> struct intel_timeline *
> __intel_timeline_create(struct intel_gt *gt,
> struct i915_vma *global_hwsp,
> @@ -106,4 +108,11 @@ int intel_timeline_read_hwsp(struct i915_request *from,
> void intel_gt_init_timelines(struct intel_gt *gt);
> void intel_gt_fini_timelines(struct intel_gt *gt);
>
> +void intel_gt_show_timelines(struct intel_gt *gt,
> + struct drm_printer *m,
> + void (*show_request)(struct drm_printer *m,
> + const struct i915_request *rq,
> + const char *prefix,
> + int indent));
> +
> #endif
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 77e76b665098..354b95c438d0 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1306,24 +1306,26 @@ static int i915_runtime_pm_status(struct seq_file *m, void *unused)
>
> static int i915_engine_info(struct seq_file *m, void *unused)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct drm_i915_private *i915 = node_to_i915(m->private);
> struct intel_engine_cs *engine;
> intel_wakeref_t wakeref;
> struct drm_printer p;
>
> - wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> + wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>
> seq_printf(m, "GT awake? %s [%d]\n",
> - yesno(dev_priv->gt.awake),
> - atomic_read(&dev_priv->gt.wakeref.count));
> + yesno(i915->gt.awake),
> + atomic_read(&i915->gt.wakeref.count));
> seq_printf(m, "CS timestamp frequency: %u Hz\n",
> - RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_hz);
> + RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);
>
> p = drm_seq_file_printer(m);
> - for_each_uabi_engine(engine, dev_priv)
> + for_each_uabi_engine(engine, i915)
> intel_engine_dump(engine, &p, "%s\n", engine->name);
>
> - intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
> + intel_gt_show_timelines(&i915->gt, &p, NULL);
> +
> + intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>
> return 0;
> }
>
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