[Intel-gfx] [PATCH 05/21] drm/i915/adl_s: Add PCH support

[Matt Roper]

On Tue, Nov 17, 2020 at 10:50:13AM -0800, Aditya Swarup wrote:
> From: Anusha Srivatsa <anusha.srivatsa at intel.com>
> 
> Add support for Alderpoint(ADP) PCH used with Alderlake-S.
> 
> v2:
> - Use drm_dbg_kms and drm_WARN_ON based on Jani's feedback.(aswarup)
> 

This patch looks okay, so

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

but I'll have some comments on later patches which are basing south
display conditions on a check for ADL-S rather than a check for ADP.
Even if we anticipate future platforms re-using ADP and needing
different logic in those areas (like we do with TGP when paired with
RKL), I think we might want to handle that differently if/when the time
comes.


Matt

> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Caz Yokoyama <caz.yokoyama at intel.com>
> Cc: Jani Nikula <jani.nikula at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Cc: Imre Deak <imre.deak at intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pch.c | 8 +++++++-
>  drivers/gpu/drm/i915/intel_pch.h | 3 +++
>  2 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
> index f31c0dabd0cc..2a6d70f247e8 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -128,6 +128,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
>  		drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
>  		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
>  		return PCH_JSP;
> +	case INTEL_PCH_ADP_DEVICE_ID_TYPE:
> +		drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
> +		drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv));
> +		return PCH_ADP;
>  	default:
>  		return PCH_NONE;
>  	}
> @@ -155,7 +159,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
>  	 * make an educated guess as to which PCH is really there.
>  	 */
>  
> -	if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
> +	if (IS_ALDERLAKE_S(dev_priv))
> +		id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
> +	else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
>  		id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
>  	else if (IS_JSL_EHL(dev_priv))
>  		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
> diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
> index 06d2cd50af0b..7318377503b0 100644
> --- a/drivers/gpu/drm/i915/intel_pch.h
> +++ b/drivers/gpu/drm/i915/intel_pch.h
> @@ -26,6 +26,7 @@ enum intel_pch {
>  	PCH_JSP,	/* Jasper Lake PCH */
>  	PCH_MCC,        /* Mule Creek Canyon PCH */
>  	PCH_TGP,	/* Tiger Lake PCH */
> +	PCH_ADP,	/* Alder Lake PCH */
>  
>  	/* Fake PCHs, functionality handled on the same PCI dev */
>  	PCH_DG1 = 1024,
> @@ -53,12 +54,14 @@ enum intel_pch {
>  #define INTEL_PCH_TGP2_DEVICE_ID_TYPE		0x4380
>  #define INTEL_PCH_JSP_DEVICE_ID_TYPE		0x4D80
>  #define INTEL_PCH_JSP2_DEVICE_ID_TYPE		0x3880
> +#define INTEL_PCH_ADP_DEVICE_ID_TYPE		0x7A80
>  #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
>  #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
>  #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
>  
>  #define INTEL_PCH_TYPE(dev_priv)		((dev_priv)->pch_type)
>  #define INTEL_PCH_ID(dev_priv)			((dev_priv)->pch_id)
> +#define HAS_PCH_ADP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
>  #define HAS_PCH_DG1(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
>  #define HAS_PCH_JSP(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
>  #define HAS_PCH_MCC(dev_priv)			(INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
> -- 
> 2.27.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795