[Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock

[Imre Deak]

This patchset replaces [1]. That version's solution to work around
broken TGL A BIOSes turned out to be papering over something. The real
root cause was the lack of a full encoder recompute/modeset during the
initial commit and leaking the incorrect link rate into the PLL
frequency calculation code. So instead of making the PLL code aware of
incorrect link rates, this patchset forces a full modeset which will
recompute the correct link rate.

Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>

[1] https://patchwork.freedesktop.org/series/82173/

Imre Deak (5):
  drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
  drm/i915: Move the initial fastset commit check to encoder hooks
  drm/i915: Check for unsupported DP link rates during initial commit
  drm/i915: Add an encoder hook to sanitize its state during init/resume
  drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref
    clock

 drivers/gpu/drm/i915/display/icl_dsi.c        | 14 ++++
 drivers/gpu/drm/i915/display/intel_ddi.c      | 18 +++++
 drivers/gpu/drm/i915/display/intel_display.c  | 33 +++++-----
 .../drm/i915/display/intel_display_types.h    | 15 +++++
 drivers/gpu/drm/i915/display/intel_dp.c       | 65 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h       |  5 ++
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 20 ++++++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 55 +++++++++++-----
 drivers/gpu/drm/i915/i915_reg.h               |  1 +
 9 files changed, 194 insertions(+), 32 deletions(-)

-- 
2.25.1