[Intel-gfx] [PATCH 01/20] drm/i915: Sort the mess around ICP TC hotplugs regs
Lucas De Marchi
lucas.demarchi at intel.com
Wed Oct 7 22:11:56 UTC 2020
On Tue, Oct 06, 2020 at 05:33:30PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
>Move the DSC stuff out from the middle of the ICP HPD register
>definitions. The location seems to have been selected by a
>dice roll.
>
>SHPD_FILTER_CNT addition also went astray due to the DSC
>mess, so we also fix that vs. ICP_TC_HPD_{SHORT,LONG}_DETECT().
>
>Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h | 215 ++++++++++++++++----------------
> 1 file changed, 107 insertions(+), 108 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 6ad9ee4243a0..efe51a4ef719 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -4618,6 +4618,110 @@ enum {
> #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
> #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
>
>+/* Icelake DSC Rate Control Range Parameter Registers */
>+#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
>+#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
>+#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
>+#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
>+#define RC_BPG_OFFSET_SHIFT 10
>+#define RC_MAX_QP_SHIFT 5
>+#define RC_MIN_QP_SHIFT 0
>+
>+#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
>+#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
>+#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
>+#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
>+
>+#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
>+#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
>+#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
>+#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
>+
>+#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
>+#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
>+#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
>+#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
>+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
>+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
>+#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
>+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
>+#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
>+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
>+
> /* VGA port control */
> #define ADPA _MMIO(0x61100)
> #define PCH_ADPA _MMIO(0xe1100)
>@@ -8305,117 +8409,12 @@ enum {
>
> #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
> #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
>-
>-#define SHPD_FILTER_CNT _MMIO(0xc4038)
>-#define SHPD_FILTER_CNT_500_ADJ 0x001D9
>-
>-/* Icelake DSC Rate Control Range Parameter Registers */
>-#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
>-#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
>-#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
>-#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
>-#define RC_BPG_OFFSET_SHIFT 10
>-#define RC_MAX_QP_SHIFT 5
>-#define RC_MIN_QP_SHIFT 0
>-
>-#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
>-#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
>-#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
>-#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
>-
>-#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
>-#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
>-#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
>-#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
>-
>-#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
>-#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
>-#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
>-#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
>-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
>-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
>-#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
>- _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
>-#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
>- _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
>-
> #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
> #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
>
>+#define SHPD_FILTER_CNT _MMIO(0xc4038)
>+#define SHPD_FILTER_CNT_500_ADJ 0x001D9
>+
that is a weird choice git 2.26 made for the diff, but looks correct. With
--color-moved (and not sure if the version made any difference, but mine
is 2.28) I could check this is plain move.
Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
Lucas De Marchi
> #define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
> SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
> #define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \
>--
>2.26.2
>
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