[Intel-gfx] [PATCH v7 06/15] drm/i915/dg1: Enable DPLL for DG1

[Aditya Swarup]

On 10/12/20 2:29 PM, Lucas De Marchi wrote:
> Add DG1 DPLL Enable register macro and use the macro to enable the
> correct DPLL based on PLL id. Although we use
> _MG_PLL1_ENABLE/_MG_PLL2_ENABLE these are rather combo phys.
> 
> While at it, fix coding style: wrong newlines and use if/else chain
> 
> v2: Rewrite original patch from Aditya Swarup based on refactors
> upstream
> 
> Bspec: 49443, 49206
> 
> Cc: Clinton Taylor <Clinton.A.Taylor at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: Aditya Swarup <aditya.swarup at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
Reviewed-by: Aditya Swarup <aditya.swarup at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 12 ++++++------
>  drivers/gpu/drm/i915/i915_reg.h               |  4 ++++
>  2 files changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 6f093e4e6b43..298321cb2bbc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -151,14 +151,14 @@ static i915_reg_t
>  intel_combo_pll_enable_reg(struct drm_i915_private *i915,
>  			   struct intel_shared_dpll *pll)
>  {
> -
> -	if (IS_ELKHARTLAKE(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
> +	if (IS_DG1(i915))
> +		return DG1_DPLL_ENABLE(pll->info->id);
> +	else if (IS_ELKHARTLAKE(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
>  		return MG_PLL_ENABLE(0);
> -
> -	return CNL_DPLL_ENABLE(pll->info->id);
> -
> -
> +	else
> +		return CNL_DPLL_ENABLE(pll->info->id);
>  }
> +
>  /**
>   * intel_prepare_shared_dpll - call a dpll's prepare hook
>   * @crtc_state: CRTC, and its state, which has a shared dpll
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0b67c868c51d..49945e33f573 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10316,6 +10316,10 @@ enum skl_power_gate {
>  #define MG_PLL_ENABLE(tc_port)	_MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
>  					   _MG_PLL2_ENABLE)
>  
> +/* DG1 PLL */
> +#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
> +					   _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
> +
>  #define _MG_REFCLKIN_CTL_PORT1				0x16892C
>  #define _MG_REFCLKIN_CTL_PORT2				0x16992C
>  #define _MG_REFCLKIN_CTL_PORT3				0x16A92C
>