[Intel-gfx] [PATCH 2/3] drm/i915: Fix MOCS PTE setting for gen9+

[Chris Wilson]

Quoting Ville Syrjala (2020-10-07 13:03:28)
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Fix up the MOCS PTE setting to really get the LLC cacheability
> from the PTE rather than hardocoding it to LLC or LLC+eLLC.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 632e08a4592b..6f771a482608 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -124,7 +124,7 @@ struct drm_i915_mocs_table {
>                    LE_1_UC | LE_TC_2_LLC_ELLC, \
>                    L3_1_UC), \
>         MOCS_ENTRY(I915_MOCS_PTE, \
> -                  LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), \
> +                  LE_0_PAGETABLE | LE_TC_0_PAGETABLE | LE_LRUM(3), \
>                    L3_3_WB)
>  
>  static const struct drm_i915_mocs_entry skl_mocs_table[] = {
> @@ -274,7 +274,7 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
>                    L3_1_UC),
>         /* Base - L3 + LeCC:PAT (Deprecated) */
>         MOCS_ENTRY(I915_MOCS_PTE,
> -                  LE_0_PAGETABLE | LE_TC_1_LLC,
> +                  LE_0_PAGETABLE | LE_TC_0_PAGETABLE,
>                    L3_3_WB),

Makes sense. Did the PAGETABLE bit carry forward into tgl? That might
fixup the new regression...

For the two given here, it certainly exists and makes a whole lot of
sense,
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris