[Intel-gfx] [PATCH] drm/i915/gt: Delay execlist processing for tgl

[Chris Wilson]

Quoting Shi, Yang A (2020-10-16 02:08:24)
> Hi Chris:
>         
>         How to determine the length of the magic delay in here?

That is the question. I started with a large udelay, played with moving
it around and shortening (5us) to try and isolate what is going on. An
arbitrary delay is awful as it is guaranteed to fail since it imposes no
barrier/serialisation, mmio often have the desired side-effect, if you
can tickle the right one.

Still this is nothing more than empirical evidence (an easily reproduced
hang that goes away), and not a hard explanation. An uncached read upon
acking the preemption event, is a pretty nasty nuisance (it's 80% of our
CS bottom half) but as compromises go, it could be far worse.
-Chris