[Intel-gfx] [RFC 09/13] drm/edid: Parse DSC1.2 cap fields from HFVSDB block

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal at intel.com>
> Sent: Thursday, October 15, 2020 4:23 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: dri-devel at lists.freedesktop.org; Shankar, Uma <uma.shankar at intel.com>;
> Kulkarni, Vandita <vandita.kulkarni at intel.com>; ville.syrjala at linux.intel.com;
> Sharma, Swati2 <swati2.sharma at intel.com>
> Subject: [RFC 09/13] drm/edid: Parse DSC1.2 cap fields from HFVSDB block

Move this also to beginning of series along with all DRM helpers.

> This patch parses HFVSDB fields for DSC1.2 capabilities of an
> HDMI2.1 sink. These fields are required by a source to understand the DSC
> capability of the sink, to set appropriate PPS parameters, before transmitting
> compressed data stream.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
> ---
>  drivers/gpu/drm/drm_edid.c  | 19 +++++++++++++++++++
> include/drm/drm_connector.h | 32 ++++++++++++++++++++++++++++++++
>  2 files changed, 51 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
> 8afb136e73f5..feee19657a7a 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4889,10 +4889,29 @@ static void
> drm_parse_hdmi_21_additional_fields(struct drm_connector *connector,  {
>  	struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
>  	u8 max_frl_rate;
> +	u8 dsc_max_frl_rate;
> 
>  	max_frl_rate = db[7] & DRM_EDID_MAX_FRL_RATE_MASK;
>  	drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
>  			     &hdmi->max_frl_rate_per_lane);
> +
> +	hdmi->dsc_1p2 = db[11] & DRM_EDID_DSC_1P2;

We should right shift them as well to get right values.

> +        hdmi->dsc_native_420 = db[11] & DRM_EDID_DSC_NATIVE_420;

Same here. Also Alignment is off.

> +	hdmi->dsc_all_bpp = db[11] & DRM_EDID_DSC_ALL_BPP;
> +
> +	if (db[11] & DRM_EDID_DSC_16BPC)
> +		hdmi->dsc_bpc_supported = 16;
> +	else if (db[11] & DRM_EDID_DSC_12BPC)
> +		hdmi->dsc_bpc_supported = 12;
> +	else if (db[11] & DRM_EDID_DSC_10BPC)
> +		hdmi->dsc_bpc_supported = 10;
> +	else
> +		hdmi->dsc_bpc_supported = 0;
> +
> +	dsc_max_frl_rate = db[12] & DRM_EDID_DSC_MAX_FRL_RATE;

This will not give correct value. Fix it.

> +	drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi->dsc_max_lanes,
> +			     &hdmi->dsc_max_frl_rate_per_lane);
> +	hdmi->dsc_total_chunk_kbytes = db[13] &
> +DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
>  }
> 
>  static void drm_parse_ycbcr420_deep_color_info(struct drm_connector
> *connector, diff --git a/include/drm/drm_connector.h
> b/include/drm/drm_connector.h index f351bf10c076..7100012f9c0f 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -213,6 +213,38 @@ struct drm_hdmi_info {
> 
>  	/** @max_lanes: supported by sink */
>  	u8 max_lanes;
> +
> +	/** @dsc_1p2: flag for dsc1.2 support by sink */
> +	bool dsc_1p2;

Add a struct for all these HDMI dsc params.

> +
> +	/** @dsc_native_420: Does sink support DSC with 4:2:0 compression */
> +	bool dsc_native_420;
> +
> +	/**
> +	 * @dsc_all_bpp: Does sink support all bpp with 4:4:4: or 4:2:2
> +	 * compressed formats
> +	 */
> +	bool dsc_all_bpp;
> +
> +	/**
> +	 * @dsc_bpc_supported: compressed bpc supported by sink : 10, 12 or 16
> bpc
> +	 */
> +	u8 dsc_bpc_supported;
> +
> +	/** @dsc_max_slices: maximum number of Horizontal slices supported
> by */
> +	u8 dsc_max_slices;
> +
> +	/** @dsc_clk_per_slice : max pixel clock in MHz supported per slice */
> +	u8 dsc_clk_per_slice;
> +
> +	/** @dsc_max_lanes : dsc max lanes supported for Fixed rate Link
> training */
> +	u8 dsc_max_lanes;
> +
> +	/** @dsc_max_frl_rate_per_lane : maximum frl rate with DSC per lane */
> +	u8 dsc_max_frl_rate_per_lane;
> +
> +	/** @dsc_total_chunk_kbytes: max size of chunks in KBs supported per
> line*/
> +	u8 dsc_total_chunk_kbytes;
>  };
> 
>  /**
> --
> 2.17.1