[Intel-gfx] [PATCH v2 01/19] drm/i915: s/PORT_TC/TC_PORT_/

[Ville Syrjälä]

On Fri, Oct 23, 2020 at 10:57:24AM -0700, Lucas De Marchi wrote:
> On Fri, Oct 23, 2020 at 04:34:02PM +0300, Ville Syrjälä wrote:
> >@@ -8352,19 +8352,19 @@ enum {
> > #define SDE_DDI_HOTPLUG_ICP(port)	(1 << ((port) + 16))
> > #define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(PORT_B) | \
> > 					 SDE_DDI_HOTPLUG_ICP(PORT_A))
> >-#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
> >+#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
> 
> At some point we may also want to add *HOTPLUG* to these macros to
> signify what it really is.  For another day.

Hmm. I have a feeling I end up removing these before the end of the
series. Ah no, that was in a followup patch I played around with.
But I'm not convinced that patch (making the IIR readout mask
calculation also based on the encoders present) is actually a
necessary thing. I guess it would be if some if the hpd bits get
repurposed and we still want to share the irq handler between
platforms with conflicting bits.

> 
> 
> Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
> 
> Lucas De Marchi
> 
> > #define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(PORT_C) | \
> > 					 SDE_DDI_HOTPLUG_ICP(PORT_B) | \
> > 					 SDE_DDI_HOTPLUG_ICP(PORT_A))
> >-#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(PORT_TC6) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC5) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
> >+#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(TC_PORT_6) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_5) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
> >
> > #define SDEISR  _MMIO(0xc4000)
> > #define SDEIMR  _MMIO(0xc4004)
> >@@ -8449,15 +8449,15 @@ enum {
> >
> > #define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
> > 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
> >-#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC4) | \
> >-					 ICP_TC_HPD_ENABLE(PORT_TC3) | \
> >-					 ICP_TC_HPD_ENABLE(PORT_TC2) | \
> >-					 ICP_TC_HPD_ENABLE(PORT_TC1))
> >+#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_4) | \
> >+					 ICP_TC_HPD_ENABLE(TC_PORT_3) | \
> >+					 ICP_TC_HPD_ENABLE(TC_PORT_2) | \
> >+					 ICP_TC_HPD_ENABLE(TC_PORT_1))
> > #define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
> > 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
> > 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
> >-#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC6) | \
> >-					 ICP_TC_HPD_ENABLE(PORT_TC5) | \
> >+#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_6) | \
> >+					 ICP_TC_HPD_ENABLE(TC_PORT_5) | \
> > 					 ICP_TC_HPD_ENABLE_MASK)
> >
> > #define _PCH_DPLL_A              0xc6014
> >@@ -10315,9 +10315,9 @@ enum skl_power_gate {
> > #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
> > #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
> > #define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	REG_BIT((phy) + 10)
> >-#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
> >+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < TC_PORT_4 ? \
> > 						       (tc_port) + 12 : \
> >-						       (tc_port) - PORT_TC4 + 21))
> >+						       (tc_port) - TC_PORT_4 + 21))
> > #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) * 2)
> > #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> > #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> >-- 
> >2.26.2
> >

-- 
Ville Syrjälä
Intel