[Intel-gfx] [PATCH] drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications

[Souza, Jose]

On Thu, 2020-10-22 at 13:48 +0100, Mun, Gwan-gyeong wrote:
> On Thu, 2020-10-22 at 12:43 +0000, Mun, Gwan-gyeong wrote:
> > 1. While testing the problematic scenario, it has not always shown
> > the
> > IOMMU DAMR related below errors on the drm-tip. 
> >    (sometimes the error messages raised, but some times it has not
> > happened on the same kernel and scenario.
> >   
> > 
> > 
> > 
> > DMAR: DRHD: handling fault status reg 2
> > DMAR: [DMA Read] Request device [00:02.0] PASID 0xffffffff fault addr
> > 0xfc001000 [fault reason 06] PTE Read access is not set
> > DMAR: DRHD: handling fault status reg 3
> > DMAR: [DMA Read] Request device [00:02.0] PASID 0xffffffff fault addr
> > 0xfc000000 [fault reason 06] PTE Read access is not set
> > 
> > 2  After applying this patch the screen glitch issues have been
> > remarkably alleviated.
> >   - Eventhough there infrequently showed the screen glitch issues.
> >   - But I agree to apply this patch as a workaround by adding the
> > explanation below.
> >  
> > 
> > 
> > 
> > 3. The dc state and PSR enable/disable scenarios has been changed by
> > this patch.
> >       
> > 
> > 
> > 
> > (1)Before applying patch
> >   enable psr 
> >     -> (front buffer updates) 
> >         -> intel_psr_flush 
> >                   ^   -> psr_force_hw_tracking_exit()
> >                   |                   : write CURSURFLIVE 
> >                   |                          |
> >                   |  (front buffer updates)  |
> >                   +--------------------------+
> > 
> >     PSR enabled -------------------------------------- -->
> >    ( DC state controlled by DMC firmware)


This scenario also causes the display to go out of DC5 too as it needs to wakeup send the PSR1 full update or the PSR2 selective update.
But I agree that doing a PSR exit will cause PSR to not be active for a few frames less than the CURSURFLIVE write.

But we already have this scenario for platforms older than gen9, so all this comments are not necessary.

> >                                    
> > 
> > 
> > 
> > 
> > 
> > 
> > 
> > 
> >  (2) After applying patch
> >   enable psr 
> >    ^  -> (front buffer updates) 
> >    |       -> intel_psr_flush
> >    |          -> psr_force_hw_tracking_exit()
> >    |               : call intel_psr_exit()
> >    |                                 -> disable psr
> >    |                                         |
> >    |                                         |
> >    +-----------------------------------------+
> > 
> > PSR enabled ---------------------------> PSR disabled
> >   ^                                          |
> >   |                                          |
> >   +------------------------------------------+
> >    ( DC state controlled by DMC firmware)
> > 
> > the repeating of enabling and disabling of PSR by the rapid screen
> > updates prevents entering of low power dc states.
> > Infereing from this scenario, it indirectly touches DC state and it
> > alleviates the issue.
> > 
> with the previous comments,
> Tested-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>
> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>

Thanks going to push this and send the IGT side changes.

> > 
> > On Fri, 2020-10-02 at 16:16 -0700, José Roberto de Souza wrote:
> > > Writes to CURSURFLIVE in TGL are causing IOMMU errors and visual
> > > glitches that are often reproduced when executing CPU intensive
> > > workloads while a eDP 4K panel is attached.
> > > 
> > > Manually exiting PSR causes the frontbuffer to be updated without
> > > glitches and the IOMMU errors are also gone but this comes at the
> > > cost
> > > of less time with PSR active.
> > > 
> > > So using this workaround until this issue is root caused and a
> > > better
> > > fix is found.
> > > 
> > > The current code is already ready to enable PSR after this exit if
> > > there is not other frontbuffer modifications.
> > > 
> > > Adding a new if block in psr_force_hw_tracking_exit() instead of
> > > reuse
> > > the else/gen8- block because the plan is to revert this workaround
> > > as soon as a better solution is found.
> > > 
> > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_psr.c | 16 +++++++++++++++-
> > >  1 file changed, 15 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 8a9d0bdde1bf..8630121dbbbe 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -1152,7 +1152,21 @@ void intel_psr_disable(struct intel_dp
> > > *intel_dp,
> > >  
> > > 
> > > 
> > > 
> > > 
> > > 
> > > 
> > > 
> > >  static void psr_force_hw_tracking_exit(struct drm_i915_private
> > > *dev_priv)
> > >  {
> > > -	if (INTEL_GEN(dev_priv) >= 9)
> > > +	if (IS_TIGERLAKE(dev_priv))
> > > +		/*
> > > +		 * Writes to CURSURFLIVE in TGL are causing IOMMU
> > > errors and
> > > +		 * visual glitches that are often reproduced when
> > > executing
> > > +		 * CPU intensive workloads while a eDP 4K panel is
> > > attached.
> > > +		 *
> > > +		 * Manually exiting PSR causes the frontbuffer to be
> > > updated
> > > +		 * without glitches and the IOMMU errors are also gone
> > > but
> > > +		 * this comes at the cost of less time with PSR active.
> > > +		 *
> > > +		 * So using this workaround until this issue is root
> > > caused
> > > +		 * and a better fix is found.
> > > +		 */
> > > +		intel_psr_exit(dev_priv);
> > > +	else if (INTEL_GEN(dev_priv) >= 9)
> > >  		/*
> > >  		 * Display WA #0884: skl+
> > >  		 * This documented WA for bxt can be safely applied
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