[Intel-gfx] [PATCH v3 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register

[Anshuman Gupta]

On 2020-10-27 at 12:41:41 +0530, Shankar, Uma wrote:
> 
> 
> > -----Original Message-----
> > From: Anshuman Gupta <anshuman.gupta at intel.com>
> > Sent: Friday, October 23, 2020 5:51 PM
> > To: intel-gfx at lists.freedesktop.org; dri-devel at lists.freedesktop.org
> > Cc: seanpaul at chromium.org; Nikula, Jani <jani.nikula at intel.com>; C,
> > Ramalingam <ramalingam.c at intel.com>; Li, Juston <juston.li at intel.com>;
> > Shankar, Uma <uma.shankar at intel.com>; Gupta, Anshuman
> > <anshuman.gupta at intel.com>
> > Subject: [PATCH v3 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register
> > 
> > Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
> > and HDCP2_AUTH_STREAM register in i915_reg header.
> > 
> > Cc: Ramalingam C <ramalingam.c at intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++
> >  1 file changed, 30 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 86a9a5145e47..cb6ec2c241f2 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9882,6 +9882,7 @@ enum skl_power_gate {
> >  					  _PORTD_HDCP2_BASE, \
> >  					  _PORTE_HDCP2_BASE, \
> >  					  _PORTF_HDCP2_BASE) + (x))
> > +
> >  #define PORT_HDCP2_AUTH(port)		_PORT_HDCP2_BASE(port, 0x98)
> >  #define _TRANSA_HDCP2_AUTH		0x66498
> >  #define _TRANSB_HDCP2_AUTH		0x66598
> > @@ -9921,6 +9922,35 @@ enum skl_power_gate {
> >  					 TRANS_HDCP2_STATUS(trans) : \
> >  					 PORT_HDCP2_STATUS(port))
> > 
> > +#define PORT_HDCP2_STREAM_STATUS(port)		_PORT_HDCP2_BASE(port,
> > 0xC0)
> > +#define _TRANSA_HDCP2_STREAM_STATUS		0x664C0
> > +#define _TRANSB_HDCP2_STREAM_STATUS		0x665C0
> > +#define TRANS_HDCP2_STREAM_STATUS(trans)	_MMIO_TRANS(trans, \
> > +
> > _TRANSA_HDCP2_STREAM_STATUS, \
> > +
> > _TRANSB_HDCP2_STREAM_STATUS)
> > +#define   STREAM_ENCRYPTION_STATUS	BIT(31)
> > +#define   STREAM_TYPE_STATUS		BIT(30)
> > +#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
> > +					(INTEL_GEN(dev_priv) >= 12 ? \
> > +					 TRANS_HDCP2_STREAM_STATUS(trans) :
> > \
> > +					 PORT_HDCP2_STREAM_STATUS(port))
> > +
> > +#define _PORTA_HDCP2_AUTH_STREAM		0x66F00
> > +#define _PORTB_HDCP2_AUTH_STREAM		0x66F04
> > +#define PORT_HDCP2_AUTH_STREAM(port)	_MMIO_PORT(port, \
> > +
> > _PORTA_HDCP2_AUTH_STREAM, \
> > +
> > _PORTB_HDCP2_AUTH_STREAM)
> 
> Should it also not be defined as the other counterparts for pre Gen12.
It has already been defined with Gen12 and Pre Gen12 annotation below
HDCP2_AUTH_STREAM should TRANS_HDCP2_AUTH_STREAM for Gen12 and
PORT_HDCP2_AUTH_STREAM for pre Gen12.
Is it something else u find it is missing ?
Thanks,
Anshuman.
> 
> > +#define _TRANSA_HDCP2_AUTH_STREAM		0x66F00
> > +#define _TRANSB_HDCP2_AUTH_STREAM		0x66F04
> > +#define TRANS_HDCP2_AUTH_STREAM(trans)	_MMIO_TRANS(trans, \
> > +
> > _TRANSA_HDCP2_AUTH_STREAM, \
> > +
> > _TRANSB_HDCP2_AUTH_STREAM)
> > +#define   AUTH_STREAM_TYPE		BIT(31)
> > +#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
> > +					(INTEL_GEN(dev_priv) >= 12 ? \
> > +					 TRANS_HDCP2_AUTH_STREAM(trans) : \
> > +					 PORT_HDCP2_AUTH_STREAM(port))
> > +
> >  /* Per-pipe DDI Function Control */
> >  #define _TRANS_DDI_FUNC_CTL_A		0x60400
> >  #define _TRANS_DDI_FUNC_CTL_B		0x61400
> > --
> > 2.26.2
>