[Intel-gfx] [PATCH] drm/i915/jsl: Disable cursor clock gating in HDR mode

[Chris Wilson]

Quoting Tejas Upadhyay (2020-10-28 11:17:31)
> Display underrun in HDR mode when cursor is enabled.
> RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
> As per W/A 1604331009, Disable cursor clock gating in HDR mode.
> 
> Bspec : 33451
> 
> Cc: Souza Jose <jose.souza at intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 32 ++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h              |  5 +++
>  2 files changed, 37 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f41b6f8b5618..73c4a43e6e31 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -541,6 +541,19 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
>                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
>  }
>  
> +/* Wa_1604331009:jsl */
> +static void
> +jsl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
> +                      bool enable)
> +{
> +       if (enable)
> +               intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
> +                              intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | CURSOR_GATING_DIS);
> +       else
> +               intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
> +                              intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~CURSOR_GATING_DIS);

intel_de_rmw(i915, CLKGATE_DIS_PSL(pipe),
	CURSOR_GATING_DIS, enable ? CURSOR_GATING_DIS : 0);
-Chris