[Intel-gfx] [PATCH 1/2] drm/i915: Make intel_{enable, disable}_sagv() static

Souza, Jose jose.souza at intel.com
Sat Sep 26 00:28:40 UTC 2020


On Fri, 2020-09-25 at 15:17 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <
> ville.syrjala at linux.intel.com
> >
> 
> intel_{enable,disable}_sagv() are no longer needed outside the
> compilation unit. Make them static.

Reviewed-by: José Roberto de Souza <jose.souza at intel.com>

> 
> Signed-off-by: Ville Syrjälä <
> ville.syrjala at linux.intel.com
> >
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++--
>  drivers/gpu/drm/i915/intel_pm.h | 2 --
>  2 files changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 34e0d22d456b..8cd62402d597 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3706,7 +3706,7 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
>   *  - All planes can enable watermarks for latencies >= SAGV engine block time
>   *  - We're not using an interlaced display configuration
>   */
> -int
> +static int
>  intel_enable_sagv(struct drm_i915_private *dev_priv)
>  {
>  	int ret;
> @@ -3740,7 +3740,7 @@ intel_enable_sagv(struct drm_i915_private *dev_priv)
>  	return 0;
>  }
>  
> -int
> +static int
>  intel_disable_sagv(struct drm_i915_private *dev_priv)
>  {
>  	int ret;
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index a2473594c2db..eab83e251dd5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -49,8 +49,6 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
>  void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
>  bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
>  			   const struct intel_bw_state *bw_state);
> -int intel_enable_sagv(struct drm_i915_private *dev_priv);
> -int intel_disable_sagv(struct drm_i915_private *dev_priv);
>  void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
>  void intel_sagv_post_plane_update(struct intel_atomic_state *state);
>  bool skl_wm_level_equals(const struct skl_wm_level *l1,
> 


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