[Intel-gfx] [PATCH v6 20/24] drm/i915/dg1: Load DMC

[Lucas De Marchi]

On Wed, Sep 30, 2020 at 09:10:43AM -0700, Matt Roper wrote:
>On Tue, Sep 29, 2020 at 11:42:30PM -0700, Lucas De Marchi wrote:
>> From: Matt Atwood <matthew.s.atwood at intel.com>
>>
>> Add support to load DMC v2.0.2 on DG1
>>
>> While we're at it, make TGL use the same GEN12 firmware size definition
>> and remove obsolete comment.
>>
>> Bpec: 49230
>>
>> v2: do not replace GEN12_CSR_MAX_FW_SIZE (from José)
>>     and replace stale comment
>>
>> Cc: Matt Roper <matthew.d.roper at intel.com>
>> Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
>
>I'm not sure if the pull request with the firmware has been sent yet,
>but the version here is correct, so

I don't think so. Yes, we will have to wait for it.

Anusha, can you send the DMC pull request?

thanks
Lucas De Marchi

>
>Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
>
>> ---
>>  drivers/gpu/drm/i915/display/intel_csr.c | 12 +++++++++---
>>  1 file changed, 9 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
>> index d5db16764619..67dc64df78a5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_csr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_csr.c
>> @@ -40,13 +40,16 @@
>>
>>  #define GEN12_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
>>
>> +#define DG1_CSR_PATH			"i915/dg1_dmc_ver2_02.bin"
>> +#define DG1_CSR_VERSION_REQUIRED	CSR_VERSION(2, 2)
>> +MODULE_FIRMWARE(DG1_CSR_PATH);
>> +
>>  #define RKL_CSR_PATH			"i915/rkl_dmc_ver2_02.bin"
>>  #define RKL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 2)
>>  MODULE_FIRMWARE(RKL_CSR_PATH);
>>
>>  #define TGL_CSR_PATH			"i915/tgl_dmc_ver2_08.bin"
>>  #define TGL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 8)
>> -#define TGL_CSR_MAX_FW_SIZE		0x6000
>>  MODULE_FIRMWARE(TGL_CSR_PATH);
>>
>>  #define ICL_CSR_PATH			"i915/icl_dmc_ver1_09.bin"
>> @@ -686,14 +689,17 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
>>  	 */
>>  	intel_csr_runtime_pm_get(dev_priv);
>>
>> -	if (IS_ROCKETLAKE(dev_priv)) {
>> +	if (IS_DG1(dev_priv)) {
>> +		csr->fw_path = DG1_CSR_PATH;
>> +		csr->required_version = DG1_CSR_VERSION_REQUIRED;
>> +		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>> +	} else if (IS_ROCKETLAKE(dev_priv)) {
>>  		csr->fw_path = RKL_CSR_PATH;
>>  		csr->required_version = RKL_CSR_VERSION_REQUIRED;
>>  		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>>  	} else if (INTEL_GEN(dev_priv) >= 12) {
>>  		csr->fw_path = TGL_CSR_PATH;
>>  		csr->required_version = TGL_CSR_VERSION_REQUIRED;
>> -		/* Allow to load fw via parameter using the last known size */
>>  		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>>  	} else if (IS_GEN(dev_priv, 11)) {
>>  		csr->fw_path = ICL_CSR_PATH;
>> --
>> 2.28.0
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795