[Intel-gfx] [PATCH v2 10/11] drm/i915: Plumb crtc_state to link training

[Ville Syrjälä]

On Wed, Sep 30, 2020 at 07:36:24PM +0300, Imre Deak wrote:
> On Wed, Sep 30, 2020 at 02:34:48AM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > 
> > Get rid of mode crtc->config usage, and some ad-hoc intel_dp state
> > usage by plumbing the crtc state all the way down to the link training
> > code.
> > 
> > Unfortunately we do have to keep some cached state in intel_dp so
> > that we can do the "does the link need retraining?" checks from
> > the short hpd handler.
> > 
> > v2: Add intel_crtc_state forward declaration
> > v3: Don't kill the PHY test code totally since it's
> >     now in the hotplug work where we can get at the states
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Reviewed-by: Imre Deak <imre.deak at intel.com>
> 
> 4 nitpicks below.
> 
<snip>
> >  static void
> > -tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
> > -				u32 level, enum intel_output_type type)
> > +tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> > +				const struct intel_crtc_state *crtc_state,
> > +				int level)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >  	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
> >  	const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
> > -	u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
> > -	int rate = 0;
> > +	u32 val, dpcnt_mask, dpcnt_val;
> > +	int n_entries, ln;
> >  
> > -	if (type == INTEL_OUTPUT_HDMI) {
> > -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > -
> > -		rate = intel_dp->link_rate;
> 
> Looks like a bugfix and then would make sense to fix it in a separate
> patch.

Didn't even notie this one. I need to check whether it's a current bug
or if I just fumbled the earlier patches somehow.

<snip>
> > @@ -4224,10 +4209,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> >  			intel_wait_ddi_buf_idle(dev_priv, port);
> >  	}
> >  
> > -	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
> > -	if (intel_dp->link_mst)
> > +	dp_tp_ctl = DP_TP_CTL_ENABLE |
> > +		    DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
> 
> Disable scrambling looks like some HW debugging feature, the HW toggles it
> automatically based on the spec. There was a recent related change
> removing setting it in intel_ddi_set_link_train().
> 
> If needed, it should be a separate change imo.

This is just a rebase fail on my part I think.
Thanks for catching it.

<snip>
> > @@ -5852,8 +5871,20 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
> >  							      intel_crtc_pch_transcoder(crtc), false);
> >  	}
> >  
> > -	intel_dp_start_link_train(intel_dp);
> > -	intel_dp_stop_link_train(intel_dp);
> > +	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
> > +		const struct intel_crtc_state *crtc_state =
> > +			to_intel_crtc_state(crtc->base.state);
> > +
> > +		/* retrain on the MST master transcoder */
> > +		if (INTEL_GEN(dev_priv) >= 12 &&
> > +		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
> > +		    crtc_state->cpu_transcoder != crtc_state->mst_master_transcoder)
> 
> Could use intel_dp_mst_is_master_trans().

Ack. Didn't remember we had such a thing.

> 
> > +			continue;
> > +
> > +		intel_dp_start_link_train(intel_dp, crtc_state);
> > +		intel_dp_stop_link_train(intel_dp, crtc_state);
> > +		break;
> > +	}
> >  
> >  	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
> >  		const struct intel_crtc_state *crtc_state =
> > @@ -5923,6 +5954,7 @@ static int intel_dp_do_phy_test(struct intel_encoder *encoder,
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +	struct intel_crtc *crtc;
> >  	u32 crtc_mask;
> >  	int ret;
> >  
> > @@ -5940,7 +5972,20 @@ static int intel_dp_do_phy_test(struct intel_encoder *encoder,
> >  
> >  	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
> >  		    encoder->base.base.id, encoder->base.name);
> > -	intel_dp_process_phy_request(intel_dp);
> > +
> > +	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
> > +		const struct intel_crtc_state *crtc_state =
> > +			to_intel_crtc_state(crtc->base.state);
> > +
> > +		/* test on the MST master transcoder */
> > +		if (INTEL_GEN(dev_priv) >= 12 &&
> > +		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
> > +		    crtc_state->cpu_transcoder != crtc_state->mst_master_transcoder)
> 
> Here too.
> 
-- 
Ville Syrjälä
Intel