[Intel-gfx] [PATCH v2] drm/i915/display/ehl: Limit eDP to HBR2

[Souza, Jose]

On Wed, 2020-09-30 at 15:56 +0000, Surendrakumar Upadhyay, TejaskumarX wrote:
> 
> -----Original Message-----
> From: Intel-gfx <
> intel-gfx-bounces at lists.freedesktop.org
> > On Behalf Of José Roberto de Souza
> Sent: 29 September 2020 01:33
> To: 
> intel-gfx at lists.freedesktop.org
> 
> Subject: [Intel-gfx] [PATCH v2] drm/i915/display/ehl: Limit eDP to HBR2
> 
> Recent update in documentation defeatured eDP HBR3 for EHL and JSL.
> 
> v2:
> - Remove dead code in ehl_get_combo_buf_trans()
> 
> BSpec: 32247
> Cc: Matt Roper <
> matthew.d.roper at intel.com
> >
> Cc: Vidya Srinivas <
> vidya.srinivas at intel.com
> >
> Signed-off-by: José Roberto de Souza <
> jose.souza at intel.com
> >
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c |  9 ++-------  drivers/gpu/drm/i915/display/intel_dp.c  | 11 ++++++++++-
>  2 files changed, 12 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4d06178cd76c..ef06b7b82be9 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1082,13 +1082,8 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  return icl_combo_phy_ddi_translations_hdmi;
>  case INTEL_OUTPUT_EDP:
>  if (dev_priv->vbt.edp.low_vswing) {
> -if (rate > 540000) {
> -*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> -return icl_combo_phy_ddi_translations_edp_hbr3;
> -} else {
> -*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> -return icl_combo_phy_ddi_translations_edp_hbr2;
> -}
> +*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> +return icl_combo_phy_ddi_translations_edp_hbr2;
> 
> As pe Bspec, ehl_edp_hbr2 does not match with icl_edp_hbr2 values. Rather I see (icl_edp_hbr2 == ehl_edp_hbr) true.

This change is not related to voltage swing tables, it is only removing a dead code as the hbr3 voltage swing table will never be used in EHL/JSL.

Yeah the voltage swing tables for EHL are not matching too, could you update it in your series updating the JSL tables?

> 
> Thanks,
> Tejas
>  }
>  /* fall through */
>  default:
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 54a4b81ea3ff..96d2c76772d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -277,13 +277,20 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
>  enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
> 
>  if (intel_phy_is_combo(dev_priv, phy) &&
> -    !IS_ELKHARTLAKE(dev_priv) &&
>      !intel_dp_is_edp(intel_dp))
>  return 540000;
> 
>  return 810000;
>  }
> 
> +static int ehl_max_source_rate(struct intel_dp *intel_dp) {
> +if (intel_dp_is_edp(intel_dp))
> +return 540000;
> +
> +return 810000;
> +}
> +
>  static void
>  intel_dp_set_source_rates(struct intel_dp *intel_dp)  { @@ -318,6 +325,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  size = ARRAY_SIZE(cnl_rates);
>  if (IS_GEN(dev_priv, 10))
>  max_rate = cnl_max_source_rate(intel_dp);
> +else if (IS_ELKHARTLAKE(dev_priv))
> +max_rate = ehl_max_source_rate(intel_dp);
>  else
>  max_rate = icl_max_source_rate(intel_dp);
>  } else if (IS_GEN9_LP(dev_priv)) {
> --
> 2.28.0
> 
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