[Intel-gfx] [PATCH 15/19] drm/i915: WA for zero memory channel

[Souza, Jose]

On Mon, 2021-04-12 at 10:05 +0100, Matthew Auld wrote:
> From: José Roberto de Souza <jose.souza at intel.com>
> 
> Commit c457d9cf256e ("drm/i915: Make sure we have enough memory
> bandwidth on ICL") assumes that we always have a non-zero
> dram_info->channels and uses it as a divisor. We need num memory
> channels to be at least 1 for sane bw limits checking, even when PCode
> returns 0, so lets force it to 1 in this case.

Missing my sob.

> 
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 584ab5ce4106..c5f70f3e930e 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -175,6 +175,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
>  			    "Failed to get memory subsystem information, ignoring bandwidth limits");
>  		return ret;
>  	}
> +	num_channels = max_t(u8, 1, num_channels);
>  
> 
> 
> 
>  	deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
>  	dclk_max = icl_sagv_max_dclk(&qi);