[Intel-gfx] [RFC 20/28] drm/i915: Use IS_GEN in execbuffer

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Stop caching the gen and use the macros to enable compile time
optimisation.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 22b8ba9c94a2..090b43be3153 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -221,7 +221,6 @@ struct i915_execbuffer {
 		struct drm_mm_node node; /** temporary GTT binding */
 		unsigned long vaddr; /** Current kmap address */
 		unsigned long page; /** Currently mapped page index */
-		unsigned int gen; /** Cached value of INTEL_GEN */
 		bool use_64bit_reloc : 1;
 		bool has_llc : 1;
 		bool has_fence : 1;
@@ -848,10 +847,9 @@ static void reloc_cache_init(struct reloc_cache *cache,
 	cache->page = -1;
 	cache->vaddr = 0;
 	/* Must be a variable in the struct to allow GCC to unroll. */
-	cache->gen = INTEL_GEN(i915);
 	cache->has_llc = HAS_LLC(i915);
 	cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
-	cache->has_fence = cache->gen < 4;
+	cache->has_fence = IS_GEN(i915, GEN_FOREVER, 3);
 	cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
 	cache->node.allocated = false;
 	cache->rq = NULL;
@@ -1113,7 +1111,8 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
 
 	err = eb->engine->emit_bb_start(rq,
 					batch->node.start, PAGE_SIZE,
-					cache->gen > 5 ? 0 : I915_DISPATCH_SECURE);
+					IS_GEN(eb->i915, 6, GEN_FOREVER) ?
+					0 : I915_DISPATCH_SECURE);
 	if (err)
 		goto err_request;
 
@@ -1192,14 +1191,13 @@ relocate_entry(struct i915_vma *vma,
 	if (!eb->reloc_cache.vaddr &&
 	    (DBG_FORCE_RELOC == FORCE_GPU_RELOC ||
 	     !reservation_object_test_signaled_rcu(vma->resv, true))) {
-		const unsigned int gen = eb->reloc_cache.gen;
 		unsigned int len;
 		u32 *batch;
 		u64 addr;
 
 		if (wide)
 			len = offset & 7 ? 8 : 5;
-		else if (gen >= 4)
+		else if (IS_GEN(eb->i915, 4, GEN_FOREVER))
 			len = 4;
 		else
 			len = 3;
@@ -1229,12 +1227,12 @@ relocate_entry(struct i915_vma *vma,
 				*batch++ = lower_32_bits(target_offset);
 				*batch++ = upper_32_bits(target_offset);
 			}
-		} else if (gen >= 6) {
+		} else if (IS_GEN(eb->i915, 6, GEN_FOREVER)) {
 			*batch++ = MI_STORE_DWORD_IMM_GEN4;
 			*batch++ = 0;
 			*batch++ = addr;
 			*batch++ = target_offset;
-		} else if (gen >= 4) {
+		} else if (IS_GEN(eb->i915, 4, GEN_FOREVER)) {
 			*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
 			*batch++ = 0;
 			*batch++ = addr;
-- 
2.27.0