[Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support

[Ville Syrjälä]

On Tue, Apr 20, 2021 at 10:48:08AM -0400, Rodrigo Vivi wrote:
> On Sun, Mar 28, 2021 at 03:57:06PM -0700, Daniele Ceraolo Spurio wrote:
> > From: Anshuman Gupta <anshuman.gupta at intel.com>
> > 
> > Add support to enable/disable PLANE_SURF Decryption Request bit.
> > It requires only to enable plane decryption support when following
> > condition met.
> > 1. PXP session is enabled.
> > 2. Buffer object is protected.
> > 
> > v2:
> > - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
> > 
> > v3:
> > - intel_pxp_gem_object_status() API changes.
> > 
> > v4: use intel_pxp_is_active (Daniele)
> > v5: rebase and use the new protected object status checker (Daniele)
> > 
> > Cc: Bommu Krishnaiah <krishnaiah.bommu at intel.com>
> > Cc: Huang Sean Z <sean.z.huang at intel.com>
> > Cc: Gaurav Kumar <kumar.gaurav at intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com>
> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/skl_universal_plane.c | 14 +++++++++++---
> >  drivers/gpu/drm/i915/i915_reg.h                    |  1 +
> >  2 files changed, 12 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index c6d7b6c054b5..b21bfb5be876 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -16,6 +16,7 @@
> >  #include "intel_sprite.h"
> >  #include "skl_scaler.h"
> >  #include "skl_universal_plane.h"
> > +#include "pxp/intel_pxp.h"
> >  
> >  static const u32 skl_plane_formats[] = {
> >  	DRM_FORMAT_C8,
> > @@ -971,7 +972,7 @@ skl_program_plane(struct intel_plane *plane,
> >  	u8 alpha = plane_state->hw.alpha >> 8;
> >  	u32 plane_color_ctl = 0, aux_dist = 0;
> >  	unsigned long irqflags;
> > -	u32 keymsk, keymax;
> > +	u32 keymsk, keymax, plane_surf;
> >  	u32 plane_ctl = plane_state->ctl;
> >  
> >  	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> > @@ -1051,8 +1052,15 @@ skl_program_plane(struct intel_plane *plane,
> >  	 * the control register just before the surface register.
> >  	 */
> >  	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> > -	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> > -			  intel_plane_ggtt_offset(plane_state) + surf_addr);
> > +	plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> > +
> > +	if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
> > +	    i915_gem_object_has_valid_protection(intel_fb_obj(fb)))
> > +		plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> > +	else
> > +		plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
> 
> This part looks right. 

The &=~ thing is pointless.

> But what should we do about the async_flip path?
> Jani? Ville? Uma? thoughts?

Presumably it can't be actually changed by an async flip? So
probbly we want to track it in the plane_state and reject async
flips if it has changed.

> 
> > +
> > +	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
> >  
> >  	if (plane_state->scaler_id >= 0)
> >  		skl_program_plane_scaler(plane, crtc_state, plane_state);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 1fe42f4a4e4b..a0313d718905 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7234,6 +7234,7 @@ enum {
> >  #define _PLANE_SURF_3(pipe)	_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
> >  #define PLANE_SURF(pipe, plane)	\
> >  	_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> > +#define   PLANE_SURF_DECRYPTION_ENABLED		REG_BIT(2)
> >  
> >  #define _PLANE_OFFSET_1_B			0x711a4
> >  #define _PLANE_OFFSET_2_B			0x712a4
> > -- 
> > 2.29.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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