[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabled

[Patchwork]

== Series Details ==

Series: drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabled
URL   : https://patchwork.freedesktop.org/series/93318/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
31185812783d drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabled
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#12: 
commit 573d7ce4f69a ("drm/i915/adlp: Add workaround to disable CMTG clock gating")

total: 0 errors, 1 warnings, 0 checks, 76 lines checked