[Intel-gfx] [PATCH V2 3/5] drm/i915/gt: Set BLIT_CCTL reg to un-cached

[Matt Roper]

On Mon, Aug 16, 2021 at 10:22:27AM +0530, Ayaz A Siddiqui wrote:
> From: Apoorva Singh <apoorva1.singh at intel.com>
> 
> Blitter commands which does not have MOCS fields rely on
> cacheability of BlitterCacheControlRegister which was mapped
> to index 0 by default.Once we changed the MOCS value of
> index 0 to L3 WB, tests like gem_linear_blits started failing
> due to change in cacheability from UC to WB.
> 
> Program and place the BlitterCacheControlRegister in
> build_aux_regs().

As noted on the previous patch, I think it might be simpler to add this
register to the engine's context workaround list.  You'd need to do so
before the check for RENDER_CLASS in the __intel_engine_init_ctx_wa, but
I think overall it might be simpler than adding a separate table to add
these extra engine context settings.

Note that we also have some other "fake" workarounds coming that will do
something similar.  For example,
  https://patchwork.freedesktop.org/patch/448804/?series=92135&rev=10


Matt

> 
> Signed-off-by: Apoorva Singh <apoorva1.singh at intel.com>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 13 +++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h      |  7 +++++++
>  2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 92141cf6f9a79..df3c5d550c46a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -372,6 +372,17 @@ add_aux_reg(struct drm_i915_aux_table *aux,
>  	return x;
>  }
>  
> +static struct drm_i915_aux_table *
> +add_blit_cctl_override(struct drm_i915_aux_table *aux, u8 idx)
> +{
> +	return add_aux_reg(aux,
> +			   "BLIT_CCTL",
> +			   BLIT_CCTL(0),
> +			   BLIT_CCTL_MOCS(idx, idx),
> +			   BLIT_CCTL_DST_MOCS_MASK | BLIT_CCTL_SRC_MOCS_MASK,
> +			   true);
> +}
> +
>  static struct drm_i915_aux_table *
>  add_cmd_cctl_override(struct drm_i915_aux_table *aux, u8 idx)
>  {
> @@ -398,6 +409,8 @@ build_aux_regs(const struct intel_engine_cs *engine,
>  		 * uncached index.
>  		 */
>  		aux = add_cmd_cctl_override(aux, mocs->uc_index);
> +		if (engine->class == COPY_ENGINE_CLASS && mocs->uc_index)
> +			aux = add_blit_cctl_override(aux, mocs->uc_index);
>  	}
>  
>  	return aux;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c8e2ca1b20796..de3cc9d66ffaa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2567,6 +2567,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  		      REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
>  		      REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
>  
> +#define BLIT_CCTL(base)	_MMIO((base) + 0x204)
> +#define   BLIT_CCTL_DST_MOCS_MASK	REG_GENMASK(14, 8)
> +#define   BLIT_CCTL_SRC_MOCS_MASK	REG_GENMASK(6, 0)
> +#define   BLIT_CCTL_DST_MOCS_SHIFT	8
> +#define   BLIT_CCTL_MOCS(dst, src)							\
> +	((((dst) << 1) << BLIT_CCTL_DST_MOCS_SHIFT) | ((src) << 1))
> +
>  #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
>  #define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
>  #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795