[Intel-gfx] [PATCH 6/8] drm/i915/fbc: Align FBC segments to 512B on glk+

[Juha-Pekka Heikkila]

Look ok to me.

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>

On 2.7.2021 23.46, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Apply the same 512 byte FBC segment alignment to glk+ as we use
> on skl+. The only real difference is that we now have a dedicated
> register for the FBC override stride. Not 100% sure which
> platforms really need the 512B alignment, but it's easieest
> to just do it on everything.
> 
> Also the hardware no longer seems to misclaculate the CFB stride
> for linear, so we can omit the use of the override stride for
> linear unless the stride is misaligned.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_fbc.c | 14 +++++++++++---
>   drivers/gpu/drm/i915/i915_reg.h          |  4 ++++
>   2 files changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 2baf58af016c..2da5295092e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -93,7 +93,7 @@ static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915,
>   	 * be 512 byte aligned. Aligning each line to 512 bytes guarantees
>   	 * that regardless of the compression limit we choose later.
>   	 */
> -	if (DISPLAY_VER(i915) == 9)
> +	if (DISPLAY_VER(i915) >= 9)
>   		return ALIGN(stride, 512);
>   	else
>   		return stride;
> @@ -334,10 +334,18 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
>   	const struct intel_fbc_reg_params *params = &fbc->params;
>   	u32 dpfc_ctl;
>   
> -	/* Display WA #0529: skl, kbl, bxt. */
> -	if (DISPLAY_VER(dev_priv) == 9) {
> +	if (DISPLAY_VER(dev_priv) >= 10) {
>   		u32 val = 0;
>   
> +		if (params->override_cfb_stride)
> +			val |= FBC_STRIDE_OVERRIDE |
> +				FBC_STRIDE(params->override_cfb_stride / fbc->limit);
> +
> +		intel_de_write(dev_priv, GLK_FBC_STRIDE, val);
> +	} else if (DISPLAY_VER(dev_priv) == 9) {
> +		u32 val = 0;
> +
> +		/* Display WA #0529: skl, kbl, bxt. */
>   		if (params->override_cfb_stride)
>   			val |= CHICKEN_FBC_STRIDE_OVERRIDE |
>   				CHICKEN_FBC_STRIDE(params->override_cfb_stride / fbc->limit);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ab2bd4837efd..7cf318d84d81 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3334,6 +3334,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>   #define   ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
>   #define   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL	(1 << 14)
>   #define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION	(1 << 23)
> +#define GLK_FBC_STRIDE		_MMIO(0x43228)
> +#define   FBC_STRIDE_OVERRIDE	REG_BIT(15)
> +#define   FBC_STRIDE_MASK	REG_GENMASK(14, 0)
> +#define   FBC_STRIDE(x)		REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
>   #define ILK_FBC_RT_BASE		_MMIO(0x2128)
>   #define   ILK_FBC_RT_VALID	(1 << 0)
>   #define   SNB_FBC_FRONT_BUFFER	(1 << 1)
>