[Intel-gfx] [PATCH] drm/i915/dg2: Memory latency values from pcode must be doubled

[Harish Chegondi]

On Fri, Aug 20, 2021 at 03:57:10PM -0700, Matt Roper wrote:
> The memory latency values returned by pcode on DG2 are in units of "2
> usec" rather than 1 usec on all other platforms.  I.e., we need to
> double the value returned by pcode to obtain the true latency value.
> 
> The bspec wording here was a bit ambiguous as to whether it wanted us to
> multiply or divide the pcode value by two, but we confirmed offline with
> the hardware team that we need to double the value the pcode gives us;
> this change is intended to support a larger range of potential latency
> values.
> 
> Bspec: 49326
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
Reviewed-by: Harish Chegondi <harish.chegondi at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 29 +++++++++++++++--------------
>  1 file changed, 15 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 65bc3709f54c..cfc41f8fa74a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2859,6 +2859,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>  		u32 val;
>  		int ret, i;
>  		int level, max_level = ilk_wm_max_level(dev_priv);
> +		int mult = IS_DG2(dev_priv) ? 2 : 1;
>  
>  		/* read the first set of memory latencies[0:3] */
>  		val = 0; /* data0 to be programmed to 0 for first set */
> @@ -2872,13 +2873,13 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>  			return;
>  		}
>  
> -		wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
> -		wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
> -				GEN9_MEM_LATENCY_LEVEL_MASK;
> -		wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
> -				GEN9_MEM_LATENCY_LEVEL_MASK;
> -		wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
> -				GEN9_MEM_LATENCY_LEVEL_MASK;
> +		wm[0] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
> +		wm[1] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
> +				GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
> +		wm[2] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
> +				GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
> +		wm[3] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
> +				GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
>  
>  		/* read the second set of memory latencies[4:7] */
>  		val = 1; /* data0 to be programmed to 1 for second set */
> @@ -2891,13 +2892,13 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>  			return;
>  		}
>  
> -		wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
> -		wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
> -				GEN9_MEM_LATENCY_LEVEL_MASK;
> -		wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
> -				GEN9_MEM_LATENCY_LEVEL_MASK;
> -		wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
> -				GEN9_MEM_LATENCY_LEVEL_MASK;
> +		wm[4] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
> +		wm[5] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
> +				GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
> +		wm[6] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
> +				GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
> +		wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
> +				GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
>  
>  		/*
>  		 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
> -- 
> 2.25.4
>