[Intel-gfx] [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width

[Srinivas, Vidya]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Sent: Wednesday, December 1, 2021 8:33 PM
> To: Srinivas, Vidya <vidya.srinivas at intel.com>
> Cc: intel-gfx at lists.freedesktop.org; Yashashvi, Shantam
> <shantam.yashashvi at intel.com>
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
> 
> On Wed, Dec 01, 2021 at 09:17:27AM +0530, Vidya Srinivas wrote:
> > PLANE_CUS_CTL has a restriction of 4096 width even though PLANE_SIZE
> > and scaler size registers supports max 5120.
> > Take care of this restriction in max_width.
> >
> > Without this patch, when 5k content is sent on HDR plane with NV12
> > content, FIFO underrun is seen and screen blanks out.
> >
> > v2: Addressed review comments from Ville. Added separate functions for
> > max_width - for HDR and SDR
> >
> > v3: Addressed review comments from Ville. Changed names of HDR and
> SDR
> > max_width functions to icl_hdr_plane_max_width and
> > icl_sdr_plane_max_width
> >
> > v4: Fixed paranthesis alignment. No code change
> >
> > Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com>
> > Signed-off-by: Yashashvi Shantam <shantam.yashashvi at intel.com>
> 
> Hmm. What's this extra sob doing here?

Hello Ville, sincere apologies. When I run checkpatch.pl I see no warnings on my host.
However patchwork keeps reporting paranthesis alignment warning.
I tried to push it multiple times after running checkpatch.pl on my host. Really sorry about that.

Regards
Vidya


> 
> > ---
> >  .../drm/i915/display/skl_universal_plane.c    | 21 +++++++++++++++----
> >  1 file changed, 17 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 28890876bdeb..e717eb58b105 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -420,9 +420,19 @@ static int icl_plane_min_width(const struct
> drm_framebuffer *fb,
> >  	}
> >  }
> >
> > -static int icl_plane_max_width(const struct drm_framebuffer *fb,
> > -			       int color_plane,
> > -			       unsigned int rotation)
> > +static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb,
> > +				int color_plane,
> > +				unsigned int rotation)
> > +{
> > +	if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
> > +		return 4096;
> > +	else
> > +		return 5120;
> > +}
> > +
> > +static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb,
> > +				int color_plane,
> > +				unsigned int rotation)
> >  {
> >  	return 5120;
> >  }
> > @@ -2108,7 +2118,10 @@ skl_universal_plane_create(struct
> > drm_i915_private *dev_priv,
> >
> >  	if (DISPLAY_VER(dev_priv) >= 11) {
> >  		plane->min_width = icl_plane_min_width;
> > -		plane->max_width = icl_plane_max_width;
> > +		if (icl_is_hdr_plane(dev_priv, plane_id))
> > +			plane->max_width = icl_hdr_plane_max_width;
> > +		else
> > +			plane->max_width = icl_sdr_plane_max_width;
> >  		plane->max_height = icl_plane_max_height;
> >  		plane->min_cdclk = icl_plane_min_cdclk;
> >  	} else if (DISPLAY_VER(dev_priv) >= 10) {
> > --
> > 2.33.0
> 
> --
> Ville Syrjälä
> Intel