[Intel-gfx] [PATCH v2 1/8] drm/i915/migrate: don't check the scratch page

[Ramalingam C]

On 2021-12-03 at 12:24:19 +0000, Matthew Auld wrote:
> The scratch page might not be allocated in LMEM(like on DG2), so instead
> of using that as the deciding factor for where the paging structures
> live, let's just query the pt before mapping it.
> 
Looks good to me.

Reviewed-by: Ramalingam C <ramalingam.c at intel.com>

> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
> Cc: Thomas Hellström <thomas.hellstrom at linux.intel.com>
> Cc: Ramalingam C <ramalingam.c at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_migrate.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 765c6d48fe52..2d3188a398dd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -13,7 +13,6 @@
>  
>  struct insert_pte_data {
>  	u64 offset;
> -	bool is_lmem;
>  };
>  
>  #define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
> @@ -41,7 +40,7 @@ static void insert_pte(struct i915_address_space *vm,
>  	struct insert_pte_data *d = data;
>  
>  	vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE,
> -			d->is_lmem ? PTE_LM : 0);
> +			i915_gem_object_is_lmem(pt->base) ? PTE_LM : 0);
>  	d->offset += PAGE_SIZE;
>  }
>  
> @@ -135,7 +134,6 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
>  			goto err_vm;
>  
>  		/* Now allow the GPU to rewrite the PTE via its own ppGTT */
> -		d.is_lmem = i915_gem_object_is_lmem(vm->vm.scratch[0]);
>  		vm->vm.foreach(&vm->vm, base, base + sz, insert_pte, &d);
>  	}
>  
> -- 
> 2.31.1
>