[Intel-gfx] [PATCH v6 1/1] drm/i915: Introduce new macros for i915 PTE

[Lucas De Marchi]

On Mon, Dec 06, 2021 at 07:36:39PM -0800, Lucas De Marchi wrote:
>On Mon, Dec 06, 2021 at 01:52:45PM -0800, Michael Cheng wrote:
>>Certain functions within i915 uses macros that are defined for
>>specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT
>>(Some architectures don't even have these macros defined, like ARM64).
>>
>>Instead of re-using bits defined for the CPU, we should use bits
>>defined for i915. This patch introduces two new 64 bit macros,
>>GEN8_PAGE_PRESENT and GEN8_PAGE_RW, to check for bits 0 and 1 and, to
>>replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.
>>
>>v2(Michael Cheng): Use GEN8_ instead of I915_
>>
>>Signed-off-by: Michael Cheng <michael.cheng at intel.com>
>>---
>>drivers/gpu/drm/i915/gt/gen8_ppgtt.c |  6 +++---
>>drivers/gpu/drm/i915/gt/intel_ggtt.c |  2 +-
>>drivers/gpu/drm/i915/gt/intel_gtt.h  |  3 +++
>>drivers/gpu/drm/i915/gvt/gtt.c       | 12 ++++++------
>>4 files changed, 13 insertions(+), 10 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>>index 9966e9dc5218..95c02096a61b 100644
>>--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>>+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>>@@ -18,7 +18,7 @@
>>static u64 gen8_pde_encode(const dma_addr_t addr,
>>			   const enum i915_cache_level level)
>>{
>>-	u64 pde = addr | _PAGE_PRESENT | _PAGE_RW;
>>+	u64 pde = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
>>
>>	if (level != I915_CACHE_NONE)
>>		pde |= PPAT_CACHED_PDE;
>>@@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr,
>>			   enum i915_cache_level level,
>>			   u32 flags)
>>{
>>-	gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
>>+	gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
>>
>>	if (unlikely(flags & PTE_READ_ONLY))
>>-		pte &= ~_PAGE_RW;
>>+		pte &= ~GEN8_PAGE_RW;
>>
>>	if (flags & PTE_LM)
>>		pte |= GEN12_PPGTT_PTE_LM;
>>diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>>index 110d3944f9a2..cbc6d2b1fd9e 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>>+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>>@@ -209,7 +209,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
>>			 enum i915_cache_level level,
>>			 u32 flags)
>>{
>>-	gen8_pte_t pte = addr | _PAGE_PRESENT;
>>+	gen8_pte_t pte = addr | GEN8_PAGE_PRESENT;
>>
>>	if (flags & PTE_LM)
>>		pte |= GEN12_GGTT_PTE_LM;
>>diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
>>index dfeaef680aac..228fbfe33cb7 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
>>+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
>>@@ -39,6 +39,9 @@
>>
>>#define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */
>>
>>+#define GEN8_PAGE_PRESENT BIT_ULL(0)
>>+#define GEN8_PAGE_RW BIT_ULL(1)
>
>ideally this would be together with other GEN8 defines, but this is
>minor.
>
>Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

and pushed, thanks

Lucas De Marchi