[Intel-gfx] [PATCH v4 12/16] uapi/drm/dg2: Introduce format modifier for DG2 clear color

[Lionel Landwerlin]

On 09/12/2021 17:45, Ramalingam C wrote:
> From: Mika Kahola <mika.kahola at intel.com>
>
> DG2 clear color render compression uses Tile4 layout. Therefore, we need
> to define a new format modifier for uAPI to support clear color rendering.
>
> Signed-off-by: Mika Kahola <mika.kahola at intel.com>
> cc: Anshuman Gupta <anshuman.gupta at intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila at intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c at intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_fb.c            | 8 ++++++++
>   drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 ++++++++-
>   include/uapi/drm/drm_fourcc.h                      | 8 ++++++++
>   3 files changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index e15216f1cb82..f10e77cb5b4a 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -144,6 +144,12 @@ static const struct intel_modifier_desc intel_modifiers[] = {
>   		.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
>   		.display_ver = { 13, 14 },
>   		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
> +	}, {
> +		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
> +		.display_ver = { 13, 14 },
> +		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC,
> +
> +		.ccs.cc_planes = BIT(1),
>   	}, {
>   		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
>   		.display_ver = { 13, 14 },
> @@ -559,6 +565,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>   		else
>   			return 512;
>   	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
>   	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
>   	case I915_FORMAT_MOD_4_TILED:
>   		/*
> @@ -763,6 +770,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
>   	case I915_FORMAT_MOD_Yf_TILED:
>   		return 1 * 1024 * 1024;
>   	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
>   	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
>   		return 16 * 1024;
>   	default:
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index d80424194c75..9a89df9c0243 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -772,6 +772,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
>   		return PLANE_CTL_TILED_4 |
>   			PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
>   			PLANE_CTL_CLEAR_COLOR_DISABLE;
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> +		return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
>   	case I915_FORMAT_MOD_Y_TILED_CCS:
>   	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>   		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -2337,10 +2339,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
>   		break;
>   	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
>   		if (HAS_4TILE(dev_priv)) {
> -			if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> +			u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> +				      PLANE_CTL_CLEAR_COLOR_DISABLE;
> +
> +			if ((val & rc_mask) == rc_mask)
>   				fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
>   			else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
>   				fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
> +			else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> +				fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
>   			else
>   				fb->modifier = I915_FORMAT_MOD_4_TILED;
>   		} else {
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 51fdda26844a..b155f69f2344 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -598,6 +598,14 @@ extern "C" {
>    */
>   #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
>   

My colleague Nanley (Cc) had some requests for clarifications on this 
new modifier.

In particular in which plane is the clear color located.


I guess it wouldn't hurt to also state for each of the new modifiers 
defined in this series, how many planes and what data they contain.

Thanks,

-Lionel


> +/*
> + * Intel color control surfaces (CCS) for DG2 clear color render compression.
> + *
> + * DG2 uses a unified compression format for clear color render compression.
> + * The general layout is a tiled layout using 4Kb tiles i.e. Tile4 layout.
> + */
> +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
> +
>   /*
>    * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>    *