[Intel-gfx] [PATCH] drm/i915: remove questionable fence optimization during copy

[Christian König]

Am 21.12.21 um 16:47 schrieb Thomas Hellström:
> Hi, Christian,
>
> On Tue, 2021-12-21 at 15:07 +0100, Christian König wrote:
>> First of all as discussed multiple times now kernel copies *must*
>> always wait
>> for all fences in a BO before actually doing the copy. This is
>> mandatory.
> This patch looks ok to me.
>
> Regarding the discussion I was just awaiting  Daniel's reply from
> yesterday:
>
> https://lists.freedesktop.org/archives/intel-gfx/2021-December/285717.html
>
> since his earlier reply
>
> https://lists.freedesktop.org/archives/intel-gfx/2021-December/285717.html
>
> contradicted your previous reply
>
> https://lists.freedesktop.org/archives/intel-gfx/2021-December/284467.html
>
> That confirmed all writes had to add an exclusive fence, and confirmed
> that starting the blit early was ok.
>
> So I was left a bit confused as to what the rules really were.
>
> So now if I understand both of you correctly, writers that want to opt
> out of implicit syncing do *not* need to add an exclusive fence. Is
> that correct?

Yes, that's a good summary of the problem.

>> Additional to that drop the handling when there can't be a shared
>> slot
>> allocated on the source BO and just properly return an error code.
>> Otherwise
>> this code path would only be tested under out of memory conditions.
> Good point.
>
>> Signed-off-by: Christian König <christian.koenig at amd.com>
> Reviewed-by: Thomas Hellström <thomas.hellstrom at linux.intel.com>
>
> Ok if I add this to drm-intel-gt-next?

Please go ahead.

Thanks,
Christian.

>
> /Thomas
>
>