[Intel-gfx] Fixes that failed to apply to v5.11-rc4

[Jani Nikula]

On Tue, 02 Feb 2021, Imre Deak <imre.deak at intel.com> wrote:
> Hi,
>
> On Tue, Feb 02, 2021 at 09:15:18AM +0200, Jani Nikula wrote:
>> On Mon, 18 Jan 2021, Jani Nikula <jani.nikula at intel.com> wrote:
>> > The following commits have been marked as Cc: stable or fixing something
>> > in v5.11-rc4 or earlier, but failed to cherry-pick to
>> > drm-intel-fixes. Please see if they are worth backporting, and please do
>> > so if they are.
>> >
>> > Conflicts:
>> > dbe13ae1d6ab ("drm/i915/pmu: Don't grab wakeref when enabling events")
>> > 9bb36cf66091 ("drm/i915: Check for rq->hwsp validity after acquiring RCU lock")
>> > 5b4dc95cf7f5 ("drm/i915/gt: Prevent use of engine->wa_ctx after error")
>> > 6a3daee1b38e ("drm/i915/selftests: Fix some error codes")
>> > 67fba3f1c73b ("drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode")
>> >
>> > Fails to build:
>> > 3170a21f7059 ("drm/i915: Only enable DFP 4:4:4->4:2:0 conversion when outputting YCbCr 4:4:4")
>> >
>> > BR,
>> > Jani.
>> 
>> Update.
>> 
>> Conflicts:
>> 5b4dc95cf7f5 ("drm/i915/gt: Prevent use of engine->wa_ctx after error")
>> 6a3daee1b38e ("drm/i915/selftests: Fix some error codes")
>> 67fba3f1c73b ("drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode")
>
> This depends on
>   1c6e527d6947 ("rm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.c")
>
>> 699390f7f026 ("drm/i915: Fix the PHY compliance test vs. hotplug mishap")
>> e7004ea4f5f5 ("drm/i915/gt: Close race between enable_breadcrumbs and cancel_breadcrumbs")
>> fed387572040 ("drm/i915/display: Prevent double YUV range correction on HDR planes")
>> 
>> Fails to build:
>> 0713eb979d2c ("drm/i915: Disable atomics in L3 for gen9")
>> f8abfda84841 ("drm/i915: Fix the MST PBN divider calculation")
>
> and this one depends on
>   a321fc2b4e60 ("rm/dp/mst: Export drm_dp_get_vc_payload_bw()")

Thanks, picked the 2+2 commits up.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center