[Intel-gfx] [PATCH] drm/i915/icl, tgl: whitelist COMMON_SLICE_CHICKEN3 register

[Sagar Ghuge]

Adding this register to whitelist will allow UMD to toggle State Cache
Perf fix disable chicken bit.

   "If this bit is enabled, RCC uses BTP+BTI as address tag in its state
   cache instead of BTI only"

which will lead to dropping unnecessary render target flushes and stall
on scoreboard.

Bspec: 11333
Bspec: 45829

Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 53f7838bd3c4..318302475c28 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1473,6 +1473,9 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
 		/* WaEnableStateCacheRedirectToCS:icl */
 		whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
 
+		/* WaAllowToDisableStateCachePerfFixFromUMD:icl */
+		whitelist_reg(w, GEN11_COMMON_SLICE_CHICKEN3);
+
 		/*
 		 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
 		 *
@@ -1533,6 +1536,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
 		/* Wa_1808121037:tgl */
 		whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
 
+		/* WaAllowToDisableStateCachePerfFixFromUMD:tgl */
+		whitelist_reg(w, GEN11_COMMON_SLICE_CHICKEN3);
+
 		/* Wa_1806527549:tgl */
 		whitelist_reg(w, HIZ_CHICKEN);
 		break;
-- 
2.29.2